Amberwave Systems Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Massachusetts Institute of Technology

Mayank T Bulsara

Anthony J Lochtefeld

Matthew T Currie

Eugene A Fitzgerald

Christopher W Leitz

Richard Charles Westhoff

Christopher J Vineis

DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Strained channel dynamic random access memory devices

Methods for forming strained channel dynamic random access memory devices

A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.

Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.

Methods for selective placement of dislocation arrays

Methods of forming dynamic random access memory trench capacitors

Dynamic random access memory trench capacitors

A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.

Method of forming multiple gate insulators on a strained semiconductor heterostructure

A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.

A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxailly growing a relaxed graded layer of In Ga As at a temperature ranging upwards from about 600&deg; C. with a subsequent process for planarization of the InGaAs alloy.

Relaxed InxGa1-xAs layers integrated with Si

A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxially growing a relaxed graded layer of In Ga As at a temperature ranging upwards from about 600&deg; C. with a subsequent process for planarization of the InGaAs alloy.

In Ga As structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of In Ga As at a temperature ranging upwards from about 600&deg; C.

Growing community of inventors

Cambridge, MA, United States of America

Mayank T Bulsara