Synopsys, Inc.

Mayank Shrivastava

Chaeryung Park

The number of scenarios analyzed for an electronic circuit is reduced to improve the processing time and resource requirements of electronic design automation processes. Each scenario is associated with a mode and a corner for the electronic circuit. Groups of scenarios corresponding to different corners for the same mode are identified. A winner scenario from each group is identified, for example, by selecting the dominant scenario from the group that covers the most number of violations in the group. The winner scenario is adjusted to account for violations of other scenarios of the group. The adjustment corresponding to a violation for a timing node from another scenario is performed by reducing the required time of the timing node in the winner scenario by a margin. The margin is determined based on timing information from the other scenario scaled to account for differences between the two scenarios.

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Sunnyvale, CA, United States of America

Mayank Shrivastava