Xilinx, Inc.

California Institute of Technology

Mayank Raj

Parag Upadhyaya

Yohan Usthavia Frans

Chuan Xie

Adebabay M Bekele

Azita Emami

Zhaowen Wang

Kun-Yung Chang

Didem Z Turker Melek

Sandeep Kumar

Suresh Ramalingam

Stanley Yuanshih Chen

Sukruth Pattanagiri Giriyappa

Gamal Refai-Ahmed

Zhaoyin D Wu

Jinyung Namkoong

Catherine Hearne

Marc Erett

Ping Chuan Chiang

Ken Chang

Sukruth Pattanagiri

Muqseed Mohammad

Vamshi Manthena

Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.

Methods and apparatuses for wavelength locking for optical wavelength division multiplexed micro-ring modulators

Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.

Methods and apparatuses for maximizing output modulation amplitude for optical wavelength division multiplexed micro-ring modulators

An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.

Circuits and methods for digital DC stabilization of optical receivers

An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

Circuits and methods for wavelength locking of optical receiver WDM filters

Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

Heterogeneous integration module comprising thermal management apparatus

Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.

Optical filter having a tapered profile

Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

High bandwidth CDR

Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

Latch-based level shifter circuit with self-biasing

An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

Integrated electrical/optical interface with two-tiered packaging

Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.

Temperature-locked loop for optical elements having a temperature-dependent response

Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) circuit for transceivers

An optical receiver circuit is disclosed, including a photodiode, an output terminal, a first amplifier stage, and an electrostatic discharge (ESD) protection circuit. The photodiode may generate a receiver current based on received optical signals. The first amplifier stage may be coupled between the photodiode and the output terminal and include a first inductor coupled between the photodiode and an input of a first inverter, and a second inductor coupled between the input of the first inverter and a first resistor. The first resistor may be coupled between the second inductor and an output of the first inverter. ESD protection circuit may be coupled to the input of the first inverter. The output terminal may generate an output signal based at least in part on the output of the first inverter.

Low power optical link

A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Method and apparatus for a phase locked loop circuit

An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal. The P coil may be configured to hide a parasitic capacitance associated with the PMOS pull-up circuit during a falling edge transition of the received data signal, and the N coil may be configured to hide a parasitic capacitance associated with the NMOS pull-down circuit during a rising edge transition of the received data signal.

Optical driver with asymmetric pre-emphasis

An example phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

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San Jose, CA, United States of America

Mayank Raj