Texas Instruments Corporation

Mayank Garg

David John Baldwin

Toru Tanaka

Shyamsunder Balasubramanian

Wenxiao Tan

Brandon J Beckham

Wei Zhang

Anant Shankar Kamath

Matthew David Romig

David Hernandez

Ganapathi Hegde

Shu-Ing Ju

Brett Earl Forejt

Arun Rao

Toshio Yamanaka

Krushal Shah

Soumi Paul

Suzanne Mary Vining

Win Naing Maung

Patrick Peter Siniscalchi

Roy Clifton Jones, Iii

Rakesh Hariharan

Bharath Kumar Singareddy

Luis Eduardo Ossa

Srijan Rastogi

David Hernandez-Garduno

Noble Narku-Tetteh

Boqiang Xiao

Vashist Bist

Vivekkumar Ramanlal Vadodariya

Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

Methods, apparatus, and systems to facilitate multi-channel isolation

A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Detection of a power state change in a serial bus repeater

Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Rejection of end-of-packet dribble in high speed universal serial bus repeaters

A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Synchronous serial interface allowing communication with multiple peripheral devices using a single chip select

Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Multi-level turn-off circuit and related methods

An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

Offset drift compensation

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Data bus signal conditioner and level shifter

A system includes a motor and a motor controller coupled to the motor. The motor controller includes a current sense circuit configured to: receive a first phase current sense measurement on a first measurement path; receive the first phase current sense measurement on a second measurement path; receive a second phase current measurement on the first measurement path; receive the second phase current on the second measurement path; average the first phase current sense measurement on the first measurement path with the first phase current sense measurement on the second path; and average the second phase current sense measurement on the first measurement path with the second phase current sense measurement on the second path.

Current sense circuit with alternating measurement paths

Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus comprising: a first transistor including a first gate, a first current terminal, and a second current terminal; a second transistor including a second gate, a third current terminal, and a fourth current terminal; the first current terminal coupled to the third current terminal; the first gate coupled to the second gate and the second current terminal; a third transistor including a third gate, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the second current terminal, third gate coupled to a voltage reference node; and a fourth transistor including a fourth gate, a seventh current terminal and an eighth current terminal, the seventh current terminal coupled to the sixth current terminal, the fourth gate coupled to the seventh current terminal and the eighth current terminal coupled to the fourth current terminal.

Methods and apparatus to reduce leakage current

A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.

Predriver short protection

An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

Common mode gain trimming for amplifier

An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.

Growing community of inventors

Murphy, TX, United States of America

Mayank Garg