Intel Corporation

Mayank Bomb

Gilbert A Neiger

Martin Guy Dixon

Srinivas Chennupaty

Jason W Brandt

Peter Lachner

Robert Valentine

David M Durham

Ravi L Sahita

Mark Jay Charney

Bret L Toll

Vedvyas Shanbhogue

Christopher J Hughes

Jesus Corbal

Barry E Huntley

Scott Dion Rodgers

Milind Baburao Girkar

Robert S Chappell

Jonathan Cannon Hall

Rajesh S Parthasarathy

Chris J Newburn

Manohar Ruben Castelino

Mark J Buxton

Jeffrey G Wiedemeier

Madhavan Parthasarathy

Anton Ivanov

Yen-Kuang (y K) Chen

Hideki (Saito) Ido

Shay Gueron

Matthew C Merten

Frank Binns

Brent Ralph Boswell

Beeman C Strong

Ofer Levy

Itamar S Kazachinsky

Tong Li

Christine E Wang

Md Asifur Rahman

Thilo Schmitt

Ilya Wagner

M D A Rahman

Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Virtualization exceptions

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Gathering and scattering multiple data elements

In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

Minimizing bandwith to compress output stream in instruction tracing systems

In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Providing status of a processing device with periodic synchronization point in instruction tracing system

An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.

Method and apparatus for generating an Advanced Encryption Standard (AES) key schedule

Method and apparatus for generating an advanced encryption standard (AES) key schedule

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Hillsboro, OR, United States of America

Mayank Bomb