International Business Machines Corporation

Maya Speiser

Omer Heymann

Moshe Leibowitz

Lidor Goren

Alex Raphayevich

Niv Amit

Ronit Bustin

Gil Noy

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Method and system for enhancing circuit design process

The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects ('WMO') may be inserted into the wiring routing on a 'WMO-per-segment' basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {'C'; one &#x201c;RC&#x201d; arrangement; 'n' times &#x201c;&#x3a0;&#x201d;-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

Method and system for modeling wiring routing in a circuit design

The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects ('WMOs') for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Method and system for embedding wire model objects in a circuit schematic design

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Tel Aviv, Israel

Maya Speiser