Hitachi, Ltd.

Fipa Frohwitter Intellectual Property Ag

Hitachi Communication Technologies, Ltd.

Other

Renesas Technology Corp.

Hitachi Communication Systems, Inc.

Htachi, Ltd.

Fipa Frohwitter International Property Ag

May Suzuki

Takashi Yano

Nobukazu Doi

Kazuyuki Hori

Satoshi Tanaka

Taizo Yamawaki

Takashi Aoyama

Akio Yamamoto

Tomonori Tanoue

Seishi Hanaoka

Manabu Kawabe

Kiyoshi Kawamoto

Joichi Saito

In a mobile communication system using a code division multiple access (CDMA) method, spreading code detection and frame/slot timing synchronization (cell search) is conducted by using a long code masked symbol. The spreading factor of the long code masked symbol is set to a value lower than spreading factors of other ordinary symbols. As a result, it becomes possible to reduce the circuit scale and power dissipation of the mobile terminal and raise the speed of cell search.

Code division multiple access mobile communication system

A wireless communication device for a communication system including data channels and control channels is disclosed. This device includes a receive section for receiving signals including data signals sent over the data channels, and control signals sent over control channels, the control signal corresponding to the data signals, a control channel demodulator for demodulating the control signals indicating at least one of the packet size and modulation method, a memory for accumulating the receive signals during the demodulation of the control signals, and a data channel demodulator for loading the receive signal from the memory, and demodulating the data signal according to the indicated at least one of the packet size and modulation method determined based on the demodulated control signals.

Baseband demodulation architecture for adaptive modulation method

A wireless communication device including: a transmitter including two DA converter units which convert two digital signals into analog signals; a combiner which combines the analog signals; a distributor which extracts a portion of the combined signal as a feedback signal; an AD converter which converts the feedback signal; an oscillator unit which supplies clock signals to operate the DA converter units and the AD converter; a first separation unit which separates the feedback signal converted by the AD converter into two signals; and a comparator unit which compares at least one of the two digital signals that are obtained by separating the inputted digital signal, or, at least one of the two digital signals that are separately inputted, with the feedback signal separated by the first separation unit, wherein the oscillator unit controls the output clock signals based on a result of the comparison by the comparator unit.

Timing adjustment method for wireless communication apparatus

A multimode wireless communication apparatus including a radio frequency unit having controllable communication mode and a control unit for periodically making the radio frequency unit operate in a mobile telephone mode and, after predetermined time, switching the mode to a wireless LAN mode, wherein if occurrence of an incoming call event is detected when the radio frequency unit is in standby reception in the mobile telephone mode, the control unit suppresses the switching to the wireless LAN mode and determines whether the communication in the mobile telephone mode should be continued or not.

Multimode wireless communication apparatus and high frequency integrated circuit therefor

Disclosed are a delay locked loop circuit capable of accurately extracting nonlinear distortion superimposed on an output of a digital predistortion type transmitter, the digital predistortion type transmitter, and a wireless base station using the same. The delay locked loop circuit outputting a smoothed signal to the variable delay element, in which delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of the variable delay element. Either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals Io, Qo undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit. In particular, an IIR filter may be used for the variable delay element.

Delay locked loop circuit, digital predistortion type transmitter using same, and wireless base station

The linearity of a transmission signal is improved in a wireless communication device by adjusting a delay difference between paths of two signals that are combined into one after modulation through the paths of different delay amounts, such as an r signal and a &#x3b8; signal in EER. A transmitter includes: a DA converter unit which converts, into analog signals, separated input digital signals; a combiner which combines the analog signals obtained through the DA conversion with each other; an distributor which extracts a feedback signal; an AD converter which converts the feedback signal into a digital signal; an oscillator unit which supplies clock signals to the converters; a first separation unit which separates the feedback signal; and a comparator unit which compares the input signal and the feedback signal, wherein the oscillator unit controls the output clock signals based on a result of the comparison.

A linear system and an EER system are used in combination such that the EER system can also be used in a cellular phone with a wide output dynamic range. In the EER system, linear control of an amplifier becomes difficult in a low output range. Thus, use of the EER system is limited to a high output range, and the linear system is used in the low output range as in the past. A power efficiency is improved while requirements of linearity are satisfied by this structure. An effective circuit structure is proposed for a switching control system for two systems. In addition, an up-converter is constituted in combination with a step-down element with high responsiveness, whereby a power supply voltage control circuit for the EER system with a wide control range and high responsiveness is provided.

Wireless communication apparatus

The hardware configuration of a baseband block in a radio communication system is reduced in gate size. Modulation/demodulation processing in a baseband block is divided into a plurality of processing units, which are connected to one another by buffer memories. The hardware gate sizes are reduced by performing processing on a plurality of channels by time division multiplexing at a speed higher than the speed at which received signals are written into the buffer memories.

Communication apparatus

The required RAM capacity is reduced by dividing an interleaving RAM in a baseband modulator into a plurality of areas and having the read side and the write side use some common areas on a time-sharing basis.

Semiconductor device for data communication control and radio communication apparatus

In order to effectively reduce power consumption of a terminal in a wireless communication apparatus upon packet communication, the wireless communication apparatus has a plurality of signal processing blocks having different signal processing periods; a buffer memory which links the signal processing blocks; and a clock control part which supplies or suspends a clock signal to each block. Each of the signal processing blocks watches whether or not there is data to be processed in the subsequent signal processing block. Based on the watched result, the clock control part controls an operation to supply or suspend the clock signal to the subsequent signal processing block.

Growing community of inventors

Kokubunji, Japan

May Suzuki