Texas Instruments Corporation

Agere Systems Inc.

Maxwell Walthour Lippitt, Iii

Byron Lovell Williams

Binghua Hu

Yuanning Chen

Scott Kelly Montgomery

Betty S Mercer

William M Moller

Stephen Arlon Meisner

Joseph William Buckfeller

C Matthew Thompson

Timothy Daniel

Lee Alan Stringer

Byron Lovell Willaims

Stephen Fredrick Clark

Fred Percy Debnam, Ii

Craig G Clabough

In a disclosed embodiment, a stacked capacitor () has bottom, middle and top metal electrode layers (A,B,C) interleaved with dielectric layers (A,B) conformally disposed within holes (A,B,C) in a protective overcoat or backend dielectric layer () over a top metal layer () of an integrated circuit (). A top electrode () contacts the top metal electrode layer (C). A bottom electrode () electrically couples an isolated part of the top metal electrode layer (C) through a bottom electrode via (A) to a first contact node (A) in the top metal layer () which is in contact with the bottom metal electrode layer (A). A middle electrode () electrically couples a part of the middle metal electrode layer (B) not covered by the top metal layer () through a middle electrode via (B) to a second contact node (B) in the top metal electrode layer (). The sidewalls of the top and middle electrode vias (A,B) are lined with insulating material to electrically isolate the metal electrode layer ends.

Multiple electrode layer backend stacked capacitor

A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.

Capacitor contact formed concurrently with bond pad metallization

An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

Methods and devices for a high-k stacked capacitor

A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.

Integrated circuit with metal silicide regions

An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.

Methods and apparatus for forming a polysilicon capacitor

Method for forming metal silicide regions in an integrated circuit

A physical vapor deposition process for maintaining the wafer below a critical temperature. The rate at which material particles are sputtered from the target and thus deposited on the wafer is controllable in response to power supplied to the target. Maintaining a desired deposition rate maintains the wafer temperature below the critical temperature.

Temperature optimization of a physical vapor deposition process to prevent extrusion into openings

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Rockwall, TX, United States of America

Maxwell Walthour Lippitt, Iii