International Business Machines Corporation

Maximino Aguilar, Jr

James Michael Stafford

Mark Richard Nutter

Sanjay Gupta

Michael Norman Day

Charles Ray Johns

James Xenidis

Roy Moonseuk Kim

Norbert M Blam

John William Gorrell, Jr

Yuan-Chang Lo

Sidney James Manning

David John Erb

Alex Chunghen Chow

Michael Stan Gowen

James Arthur Brewer

Charles Edward Tysor

Mark Plunkett

Michael A Paolini

Harm Peter Hofstee

Masakazu Suzuoki

David Jones Craft

Akiyuki Hatakeyama

Michael Edward Criscolo

Raymond F Romon

David Roy Limpert

Robert Ellington Millican, Jr

A mechanism is provided for generating event notifications for offline characters from within a persistent world online game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent composes an event notification message and sends the message to the offline player. Event notification messages may include images, voice (text-to-speech), sound, or video. Offline players may receive event notifications at various messaging clients, such as personal computers and wireless telephones. A notification server may transmit the event notifications via existing communications channels, such as electronic mail, facsimile, instant messaging, text messaging, and voice communications.

Virtual world event notifications from within a persistent world game

A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.

Adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures

An approach that uses a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.

Task switching based on a shared memory condition associated with a data request and detecting lock line reservation lost events

Code handling, such as interpreting language instructions or performing 'just-in-time' compilation, is performed using a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.

Processor dedicated code handling in a multi-processor environment

A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent may generate game events on behalf of the offline player. The player agent may also receive messages from an offline player. The messages may include commands for adding, removing, or editing offline player rules. A message may also include a command to view a list of rules or fire a one-time execution of a rule upon receipt. Therefore, a player may contribute to the persistent virtual world even when offline by sending commands using a messaging client or Web browser.

Configure offline player behavior within a persistent world game

A method for visually displaying an indicator for preceding and succeeding source code lines being executed within a graphical debugging environment. The method includes displaying within a GUI source code lines for a segment of currently examined source code, displaying a visual indicator that is associated with a presently examined source code line, and determining a previously examined source code line, wherein the location of the previously examined line of source code is determined by the use of information that is associated with the previously examined line of source code. The method further includes displaying a visual indicator that is associated with the previously examined line of source code, determining a next source code line that is to be examined, and displaying a visual indicator that is associated with the next source code line that is to be examined.

Method for visually indicating preceding and succeeding source code lines that are executed in a graphical debugging environment

A computer implemented method and system for optimizing thermal performance of a computer system. An identification of a set of processor cores associated with the computer system is made and a thermal index is requested for each of the set of processor cores to form a set of thermal indexes. Proximity information and conductive property information associated with the set of processors is loaded and software is mapped to execute on an optimal processor core form the set of processor cores based the set of thermal indexes, proximity information, and conductive property information.

Optimizing thermal performance using thermal flow analysis

Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search.

Asynchronous linked data structure traversal

A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Managing a plurality of processors as devices

A computer implemented method, data processing system, and computer usable code are provided for generation of hardware thermal profiles for a set of processors. Sampling is performed of the thermal states of the set of processors during the execution of a set of workloads to create sampled information. The sampled information and thermal characteristics of the set of processors are combined and a thermal index is generated based on the sampled information and characteristics of the set of processors.

Generation of hardware thermal profiles for a set of processors

Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.

Loading software on a plurality of processors

A computer implemented method, data processing system, computer usable code, and apparatus are provided for generation of software thermal profiles for applications executing on a set of processors. Sampling is performed of the hardware operations occurring in a set of processors during the execution of a set of workloads to create sampled information. A thermal index is then generated based on the sampled information.

Generation of software thermal profiles executed on a set of processors using processor activity

Grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.

Grouping processors and assigning shared memory space to a group in a heterogeneous computer environment

A method for managing multiple processors in the execution of one or more processes in a task-based library platform. The one or more processes are partitioned into highly granulized sub-tasks from a library calling process, whereby each sub-task has a protection attribute associated with it. The protection attribute designates processing resources that a processor may use in the execution of the sub-task. The sub-tasks are placed in a central task queue, whereby idling processors in the multiple processor system obtain consecutive sub-tasks in the queue until all the processes have been executed. Each processor executes a sub-task using only those processing resources that have been designated as being available by the protection attribute of the sub-task. The atomic execution results of the one more sub-tasks may then be combined into an execution result for the process. Also provided is a task-based library for processor management.

Operating system kernel-assisted, self-balanced, access-protected library framework in a run-to-completion multi-processor environment

A computer implemented method, data processing system, computer usable code, and apparatus are provided for optimizing the thermal performance of a computer system. A set of processor cores associated with the computer system are identified. A thermal index is requested for each of the set of processor cores and the processor cores are ranked based on the thermal index. Software is then mapped to execute on an optimal processor core form the set of processor cores based on the ranking.

Growing community of inventors

Austin, TX, United States of America

Maximino Aguilar, Jr