Infineon Technologies Austria Ag

Maximilian Treiber

Franz Hirler

Daniel Tutuc

Hans Weber

Andreas Voerckel

Hans-Joachim Schulze

Anton Mauder

Johannes Georg Laven

Werner Schustereder

Ingo Muri

Christian Fachmann

Joachim Weyers

A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

Superjunction transistor device

Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

Method for producing a superjunction device

A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.

Method for forming a superjunction transistor device

A semiconductor device includes a transistor. The transistor includes a source region adjacent to a first main surface of a semiconductor substrate, the source region being electrically coupled to a source terminal via a source contact. The transistor further includes a gate electrode over the first main surface of the semiconductor substrate, a drain region adjacent to a second main surface of the semiconductor substrate, and a conductive plate vertically adjacent to the gate electrode. The conductive plate is in electrical contact with the source terminal. The transistor further includes an insulating material arranged between the conductive plate and the source contact in a direction parallel to the first main surface.

Semiconductor device having a transistor and a conductive plate

Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.

A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.

Charge compensation semiconductor devices

A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.

Forming a superjunction transistor device

A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor.

Semiconductor device and a manufacturing method therefor

A field-effect semiconductor device includes a semiconductor body having a first semiconductor region of a first conductivity type, a first side, an edge delimiting the semiconductor body in a direction substantially parallel to the first side, an active area, and a peripheral area arranged between the active area and the edge. A first metallization is arranged on the first side, and a second metallization is arranged opposite the first metallization and in Ohmic connection with the first semiconductor region. In the active area, the semiconductor body further includes: a plurality of drift portions of the first conductivity type alternating with compensation regions of a second conductivity type, the drift portions being in Ohmic connection with the first semiconductor region, the compensation regions being in Ohmic connection with the first metallization and having in a vertical direction perpendicular to the first side a vertical extension.

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Munich, Germany

Maximilian Treiber