International Business Machines Corporation

Applied Materials, Inc.

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Freescale Semiconductor,inc.

Université Grenoble Alpes

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Maxime Darnon

Qinghuang Lin

Lawrence Alfred Clevenger

Anthony David Lisi

Satyanarayana Venkata Nitta

Pratik P Joshi

Olivier Joubert

Gerald Warren Gibson, Jr

Satya Venkata Nitta

Jeffrey P Gambino

Carl John Radens

Daniel C Edelstein

Shom Ponoth

Ying Di Zhang

Timothy Joseph Dalton

Elbert Emin Huang

Nicolas Posseme

Bernard Dieny

Samer Banna

Rainer Klaus Krause

Lei Lian

Kevin M Prettyman

Benjamin Schwarz

Gerd Pfeiffer

Gabriele Navarro

Brian Christopher Sapp

Laurent J Vallier

Pak Leung

Ryan M Martin

Samuel S S Choi

Cecile Gourgon

Thierry Chevolleau

Jérémy Gilbert Maurice Pereira

Kevin Menguelti

Erwine Maude Pargon

Olivier Desplats

Cécile Gourgon

An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.

Photovoltaic module with a controllable infrared protection layer

A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

Method for manufacturing a resistive device for a memory or logic circuit

A method for producing patterns includes inclined flanks from a face of a substrate. A protective mask is formed covering at least two masked areas of the face of the substrate and defining at least one intermediate space. An inclined flank is plasma etched from each masked area, wherein the etching forms continuous passivation layer on the inclined flanks producing autolimitation of the etching when the inclined flanks join each other. The etching is carried out in a chamber and includes the introduction into the chamber of a gas additional to the plasma. The additional gas includes molecules of a chemical species participating in the formation of the passivation layer, the quantity of gas in the chamber being controlled so that the chamber contains a quantity of molecules of the species sufficient to form the passivation layer continuously.

Multi-level autolimitating etching method

An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

Interconnect structures containing a photo-patternable low-k dielectric with a curved sidewall surface

In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Embedded test structure for trimming process control

Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Methods for fabrication of an air gap-containing interconnect structure

Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Structures and methods for air gap integration

The present disclosure relates to a structure comprising and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.

Methodology for evaluation of electrical characteristics of carbon nanotubes

The present disclosure relates to a structure comprising

A single damascene or dual damascene interconnect structure fabricated with a photo-patternable low-k dielectric (PPLK) which is cured after etching. This method prevents the PPLK damage and the tapering of the edges of the interconnect structure. In one embodiment, the method of the present invention includes depositing a photo-patternable low-k (PPLK) material atop a substrate. The at least one PPLK material is patterned, creating a single damascene structure. For dual damascene structures, a second PPLK layer is coated and patterned. An etch process is performed to transfer the pattern from the PPLK material into at least a portion of the substrate. A diffusion liner and a conductive material can be deposited after the etch process. The resulting structure is cured anytime after etching in order to transform the resist like PPLK into a permanent low-k material that remains within the structure.

Methods for photo-patternable low-k (PPLK) integration with curing after pattern transfer

Air gap-containing interconnect structure having photo-patternable low k material

Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH, H, CH, CH, SiH, and HS. It has been found that patterning a magnetic tunnel junction with an oxidizer-free gas mixture comprising hydrogen maintains the integrity of the magnetic tunnel junction without producing harmful conductive residue.

Method of patterning of magnetic tunnel junctions

The present disclosure relates to a method of patterning a photosensitive material on a polymeric fill matrix comprising at least one latent photoacid generator; and a structure prepared according to said method. The method comprises:

Method of patterning photosensitive material on a substrate containing a latent acid generator

The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising:

Selective etch back process for carbon nanotubes intergration

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Grenoble, France

Maxime Darnon