Samsung Electronics Co., Ltd.

Intel Corporation

Nvidia Corporation

Maxim Lukyanov

Boris Beylin

Alexander Grosul

Hong Jiang

Guei-Yuan Lueh

Mitchell K Alsup

Ping Liu

Xuefeng Zhang

Yuenian Yang

Xiaoying He

John Wakefield Brothers

Santosh Abraham

Robert Steven Glanville

Yang Jiao

Lingjie Xu

Alex Grosul

A method for improving power, performance, area (PPA) for mixed precision computations in a processing environment. The method includes determining a braiding factor as a number of units of work encoded into a physical thread. A value of the braiding factor is determined based on a mix of precision requirements presented for individual units of work. Units of work are classified as instructions for applied code transformation based on associated precision requirements for the processing environment. Instruction inputs from specified registers are packed together into a destination register according to the determined value of the braiding factor. The packed instructions presented in vector form are executed with an instruction set architecture configured for executing packed instructions of different precisions.

Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices

A method for reducing execution of redundant threads in a processing environment. The method includes detecting threads that include redundant work among many different threads. Multiple threads from the detected threads are grouped into one or more thread clusters based on determining same thread computation results. Execution of all but a particular one thread in each of the one or more thread clusters is suppressed. The particular one thread in each of the one or more thread clusters is executed. Results determined from execution of the particular one thread in each of the one or more thread clusters are broadcasted to other threads in each of the one or more thread clusters.

Redundancy elimination in single instruction multiple data/thread (SIMD/T) execution processing

A method for computing in a thread-based environment provides manipulating an execution mask to enable and disable threads when executing multiple conditional function clauses for process instructions. Execution lanes are controlled based on execution participation for the process instructions for reducing resource consumption. Execution of particular one or more schedulable structures that include multiple process instructions are skipped based on the execution mask and activating instructions.

Control flow in a thread-based environment without branching

A computer system may generate a plurality of component kernels, which are to be linked during the runtime. The system may determine whether a combined kernel K is present in response to receiving a first request to retrieve the combined kernel K. The system may compose the combined kernel K from the selected component kernels of the plurality of component kernels during the runtime if the combined kernel is not already present.

Dynamic linking and loading of post-processing kernels

One embodiment of the present invention sets forth a technique for placing texture barrier instructions within a thread program to advantageously enable efficient and correct operation of the thread program. A thread program compiler statically determines a pending request count needed to progress beyond a particular texture barrier instruction, which blocks execution of subsequent instructions that depend on previously requested data. Each instance of the thread program blocks execution at the barrier instruction until a pending request count condition is satisfied. This technique may advantageously reduce power consumption in a graphics processing unit by eliminating power consumption associated with conventional, generalized scoreboard resources.

Efficient placement of texture barrier instructions

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Sunnyvale, CA, United States of America

Maxim Lukyanov