Allegro Microsystems, LLC

Maxim Klebanov

Sundar Chetlur

Washington Lamar

Paolo Campiglio

Yen Ting Liu

Chung C Kuo

Harianto Wong

Richard B Cooper

William P Taylor

Samridh Jaiswal

Devon Fernandez

Cory Voisine

Kenneth Snowdon

James McClay

Thomas S Chung

Sebastian Courtney

Sagar Saxena

Hsuan-Jung Wu

Michael C Doogue

Alexander Latham

Bryan Cadugan

Jeffrey Eagen

Juin Jei Liou

William Wilkinson

Zhixin Wang

Yu-Ming Wang

Wei Liang

Felix Palumbo

Yu-Chun Li

In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.

Flash memory cell structure having separate program and erase electron paths

In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the MR layers using the first hard mask; depositing a second hard mask on a first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching the MR element using the second hard mask; etching portions of the first hard mask down to a top MR layer of the MR element; and depositing a conducting material on the top MR layer to form an electroconductive contact.

Fabricating an electroconductive contact on a top layer of a tunneling magnetoresistance element using two hard masks

In one aspect, a method includes depositing a capping layer on a semiconductor device structure. The semiconductor device includes a plurality of tunneling magnetoresistance (TMR) elements, a corresponding one hard mask on each TMR element, a metal layer, and a plurality of electroconductive vias directly connecting the TMR elements to the metal layer. The method further includes depositing an insulator on the capping layer, depositing a first photoresist on the insulator, patterning the first photoresist using photolithography to expose portions of the insulator, etching the exposed portions of the insulator and the hard masks to expose top surfaces of the TMR elements, stripping the first photoresist, and depositing a conducting material on the top surfaces of the TMR elements to form an electroconductive contact.

Fabricating an electroconductive contact on a top surface of a tunneling magnetoresistance element

In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

Double-diffused metal-oxide-semiconductor transistor including a recessed dielectric

A Schottky diode includes a substrate having a first type dopant, a buried layer within the substrate and having a second type dopant, an epitaxial layer above the buried layer and having the second type dopant, a plurality of rings within the epitaxial layer and having the first type dopant, wherein the plurality of rings comprises an L-shaped ring, a shallow trench isolation (STI) layer at the top region of the epitaxial layer, an anode, a cathode spaced from the anode by the STI layer, and wherein the buried layer has an open region substantially vertically aligned with the anode.

Schottky diode with tunable blocking voltage

An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

Dual circuit digital isolator

In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.

Multi-terminal devices using magnetoresistance elements

In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

Snapback electrostatic discharge protection device with tunable parameters

In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element. In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.

Fabricating planarized coil layer in contact with magnetoresistance element

Methods and apparatus for a magnetoresistive (MR) sensor including a seed layer having a CoFe layer for canceling hysteresis in the MR sensor. The MR stackup can include a free layer and a reference layer. The seed layer having CoFe provides a desired texturing of the stackup to cancel hysteresis effects.

Magnetoresistive sensor having seed layer hysteresis suppression

In one aspect, a method includes forming a metal layer on a substrate, wherein the metal layer comprises a first coil, forming a planarized insulator layer on the metal layer, forming at least one via in the planarized insulator layer, depositing a magnetoresistance (MR) element on the planarized insulator layer, and forming a second coil extending above the MR element. The at least one via electrically connects to the metal layer on one end and to MR element on the other end.

Fabricating a coil above and below a magnetoresistance element

Methods and apparatus for a sensor including a series of tunneling magnetoresistance (TMR) pillars and a heatsink adjacent to at least one of the TMR pillars, where the heatsink comprises Titanium Nitride (TiN).

TMR assembly having a heat sink

An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

Multi-layer integrated circuit with enhanced thermal dissipation using back-end metal layers

An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

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Newton, MA, United States of America

Maxim Klebanov