Advanced Micro Devices Corporation

Ati Technologies Ulc

Other

Globalfoundries Inc.

Maxat Touzelbaev

Gamal Refai-Ahmed

Raj N Master

Seah Sun Too

Yizhang Yang

Janet Kirkland

Bryan Black

Frank G Kuechenmeister

Tek Seng Tan

Hsiang Wan Liau

Samuel D Naffziger

Michael Zhouying Su

Baomin Liu

Stanley Ossias

An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

Performance state boost for multi-core integrated circuit

A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.

Stacked semiconductor chips with thermal management

Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

Thermal interface material with support structure

A valley-fill circuit with active conduction angle control allows use of a single storage capacitor instead of two. The capacitor is charged to the maximum voltage of the AC cycle, which makes possible use of low-capacitance high-voltage low ESR capacitors, increases energy storage density and decreases circuit footprint. This makes it feasible to use ceramic capacitors, such as a multilayer ceramic (MLCC), polyethylene, polypropylene, or any suitable capacitor type in addition to electrolytic capacitors. This improves the operational longevity and reduces the footprint of the circuitry.

Valley-fill power factor correction circuit with active conduction angle control

Various computing center control and cooling apparatus and methods are disclosed. In one aspect, a method of controlling plural processors of a computing system is provided. The method includes monitoring activity levels of the plural processors over a time interval to determine plural activity level scores. The plural activity level scores are compared with predetermined processor activity level scores corresponding to preselected processor operating modes to determine a recommended operating mode for each of the plural processors. Each of the plural processors is instructed to operate in one of the recommended operating modes.

Computing center power and cooling control apparatus and method

Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.

Lid attach process

Embodiments of systems and methods for improved measurement of transient thermal responses in electronic systems are described herein. Embodiments of the disclosure use the known thermal transfer function of an electronic system to generate an equivalent resistor-capacitor (RC) network having a dynamic response that is identical to a given power excitation as the actual electronic system would have to that power excitation. Using the analogy between thermal and electrical systems, a Foster RC network is constructed, comprising a plurality of RC stages in which resistors and capacitors are connected in parallel. Subsequently, the analog thermal RC network is converted into an infinite impulse response (IIR) digital filter, whose coefficients can be obtained the Z-transform of the analog thermal RC network. This IIR digital filter establishes the recursive relationship between temperature output at the current time step and measured power input at the previous time step. Using this IIR digital filter, temperature response subject to arbitrary time-dependent power can be calculated in very small amount of time compared with prior art methods.

Transient thermal modeling of multisource power devices

Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure.

Semiconductor chip thermal interface structures

Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

Void reduction in indium thermal interface material

Various heat sinks, method of use and manufacture thereof are disclosed. In one aspect, a method of providing thermal management for a circuit device is provided. The method includes placing a heat sink in thermal contact with the circuit device wherein the heat sink includes a base member in thermal contact with the circuit device, a first shell coupled to the base member that includes a first inclined internal surface, a lower end and first plurality of orifices at the lower end to enable a fluid to transit the first shell, and at least one additional shell coupled to the base member and nested within the first shell. The at least one additional shell includes a second inclined internal surface and a second plurality of orifices to enable the fluid to transit the at least one additional shell. The fluid is moved through the first shell and the at least one additional shell.

Heat sink for a circuit device

Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes placing a gel-type thermal interface material in a preselected pattern on a semiconductor chip that is coupled to a substrate. The preselected pattern of gel-type thermal interface material is allowed to partially set up. Additional thermal interface material is placed on the semiconductor chip and cured.

Method for decreasing surface delamination of gel-type thermal interface material by management of the material cure temperature

Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer.

Growing community of inventors

San Jose, CA, United States of America

Maxat Touzelbaev