Massachusetts Institute of Technology

Analog Devices,inc.

Max Shulaker

Mindy Deanna Bishop

Gage Krieger Hills

Christian Lau

Denis Michael Murphy

Yosi Stein

Samuel Fuller

Tathagata Srimani

A monolithic, three-dimensional (3D) integrated circuit (IC) device includes a sensing layer, a memory layer, and a processing layer. The sensing layer includes a plurality of carbon nanotube field-effect transistors (CNFETs) that are functionalized with at least 50 functional materials to generate data in response to exposure to a gas. The memory layer stores the data generated by the plurality of CNFETs, and the processing layer identifies one or more components of the gas based on the data generated by the plurality of CNFETs.

Systems, devices, and methods for gas sensing

Monolithic 3D integrated circuit for gas sensing and method of making and system using

A carbon nanotube field effect transistor (CNFET), that has a channel formed of carbon nanotubes (CNTs), includes a layered deposit of a nonstoichiometric doping oxide (NDO), such as HfO, where the concentration of the NDO varies through the thickness of the layer(s). An n-type metal-oxide semiconductor (NMOS) CNFET made in this manner can achieve similar ON-current, OFF-current, and/or threshold voltage magnitudes to a corresponding p-type metal-oxide semiconductor (PMOS) CNFET. Such an NMOS and PMOS can be used to achieve a symmetric complementary metal-oxide semiconductor (CMOS) CNFET design.

Tunable doping of carbon nanotubes through engineered atomic layer deposition

System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

Systems and methods for designing integrated circuits

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L) or contact length (L). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6&#xd7; improvement to EDP compared to top-gate CNFETs.

Back-gate field-effect transistors and methods for making the same

A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.

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Weston, MA, United States of America

Max Shulaker