International Business Machines Corporation

Globalfoundries Inc.

Siemens Aktiengesellschaft

Other

Kabushiki Kaisha Toshiba

Max Gerald Levy

James Albert Slinkman

Timothy Dooling Sullivan

Richard A Phelps

Victor R Nastasi

Steven H Voldman

Alvin Jose Joseph

Alan Bernard Botula

David C Thomas

Matthew D Moon

Gary L Milo

Jeffrey P Gambino

William R Tonti

John J Ellis-Monaghan

Yun Shi

Michael Joseph Zierak

Randy Lee Wolf

Natalie Barbara Feilchenfeld

Max L Lifson

Shawn A Adderly

Samantha D DiStefano

Manfred Hauf

Claude Louis Bertin

Russell J Houghton

Erik L Hedberg

Santosh Sharma

Bernhard Fiegl

Paul Christian Parries

Matthew J Sendelbach

George R Goth

William C Wille

Walter Glashauser

Rick L Mohler

Anthony C Speranza

Dinh Dang

Thai Doan

Jessica Anne Levy

Alan Frederick Norris

Wayne M Trickle

Steven S Williams

Jed Hickory Rankin

Son Van Nguyen

Wayne Frederick Ellis

Donald Francis Canaperi

Hirofumi Inoue

Mahadevaiyer Krishnan

Theodore James Letavic

Michael Straight Hibbs

William J Cote

Masami Aoki

Johann Alsmeier

Louis DeWolf Lanzerotti

Bruce Walter Porth

Rangarajan Jagannathan

BethAnn Rainey

Dale Warner Martin

Martin Knaipp

Gerd Pfeiffer

James Anthony O'Neill

Rainer Minixhofer

Georg Roehrer

Markus M Kirchhoff

Donna Rizzone Cote

James Anthony Tornello

Hubert Enichlmair

Frank Prein

Kenneth Christopher Racette

Brennan J Brown

Emily E Fisch

Michael Lawrence Gautsch

Juergen Wittmann

Wolfgang Bergner

BethAnn Lawrence

Paul C Buschner

Tinghao T Wang

Uma Satyendra

Bernard Loeffler

Jong-Mun Park

An apparatus and an associated method. The apparatus includes a chuck, an array of three or more ultrasonic sensors, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

Centering substrates on a chuck

Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Tapered gate oxide in LDMOS devices

An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.

Structures with contact trenches and isolation trenches

Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Semiconductor device with metal extrusion formation

An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor.

Apparatus and method for centering substrates on a chuck

Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

An apparatus and method for leak detection of coolant gas from a chuck. The apparatus includes a chuck having a top surface and configured to clamp a substrate to the top surface, the chuck having one or more recessed regions in the top surface, the recessed regions configured to allow a cooling gas to contact a backside of the substrate; a cooling gas inlet and a cooling gas outlet connected to the one or more recessed regions; a first measurement device connected to the cooling gas inlet and configured to measure a first amount of cooling gas entering the cooling gas inlet and a second measurement device connected to the cooling gas outlet and configured to measure a second amount of cooling gas exiting from the cooling gas outlet; and a controller configured to determine a difference between the first amount of cooling gas and the second amount of cooling gas.

Method and apparatus for detecting foreign material on a chuck

Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

Controlled metal extrusion opening in semiconductor structure and method of forming

Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure.

Low leakage, high frequency devices

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method

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Essex Junction, VT, United States of America

Max Gerald Levy