Imagination Technologies Limited

Max Freiburghaus

Robert McKemey

Sam Elliott

Thomas Michael Rose

Emiliano Morini

Robert McKerney

Robert Mckemey

A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by The hardware logic comprises a plurality of multipliers and adders arranged to implement a m-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Iterative estimation hardware

An adder and a method for calculating 2+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2+x for x<0 and 2≤|x|<2; a second path configured to calculate 2+x for |x|<2; a third path configured to calculate 2+x for |x|≥2; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

Floating point adder

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kdifference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Verification of hardware design for integrated circuit implementing polynomial input variable function

An adder and a method for calculating 2+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2+x for x&#x3c;0 and 2&#x2264;|x|&#x3c;2; a second path configured to calculate 2+x for |x|&#x3c;2; a third path configured to calculate 2+x for |x|&#x2265;2; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

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London, United Kingdom

Max Freiburghaus