Microsoft Technology Licensing, LLC

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Max Earl Nielsen

Bouchaib Cherif

Joshua A Strong

Jose M Acevedo

Ian G Thompson

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Trap circuits for use with differential capacitively-coupled resonant clock networks

Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.

Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib

Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

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Max Earl Nielsen