Amazon Technologies, Inc.

Max Chvalevsky

Uri Leder

Itamar Bonne

Ori Ariel

Simaan Bahouth

Assaf Fainer

Itai Kahana

Hani Assaf

Yefim Fainstein

Systems and methods are provided to generate time data according to a nominal frequency and based on an available frequency. A hardware clock of the system can operate according to the available frequency. The system can identify a difference between the available frequency and a nominal frequency. Based on the difference, the system can generate time data according to the nominal frequency. To generate the time data, for each clock cycle of a plurality of clock cycles according to the available frequency, the system can determine whether to increment or maintain a value of the time data for a prior clock cycle of the plurality of clock cycles. The system can perform one or more functions based on the time data.

Configurable system counter based on a hardware clock frequency

Cover properties are extended in formal verification to reach an effective end-of-test stage for a design under test. A formal verification task for a design under test may be received at a verification system. A cover property asserted in the formal verification task may be identified. An additional condition may be implemented for the identified cover property to extend the identified cover property to cause performance of the formal verification task to generate a trace to reach an effective end-of-test stage for the design under test in the event of a failure of the cover property.

Extending cover properties in formal verification to generate failure traces that reach end-of-test

Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

Executing instruction sequences generated from software interactions as part of formal verification of a design under test

A fuzzy scoreboard can compute, using a signature function, a first signature of an expected data stream associated with an input data stream that is being inputted to a design-under-test (DUT) for a datapath test. The first signature of the expected data stream can be stored without storing the expected data stream. The fuzzy scoreboard can also compute, using the same signature function, a second signature of an output data stream that is outputted from the DUT during the datapath test. The first signature can be compared with the second signature to determine whether there is a match. Storing the first signature of the expected data stream without storing the expected data stream can reduce the memory space consumed by the fuzzy scoreboard.

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Mevaseret Zion, Israel

Max Chvalevsky