Motorola Corporation

Telonics, Inc.

Mavin C Swapp

Milo W Frisbie

Hugh W Littlebury

Larry A Nickerson

David Wiley Beaty

Charles R Collis

Derek Johnson

John L Peterson

A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10'), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10') converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Method for measuring time and structure therefor

Throughput and accuracy of testing of a semiconductor device is improved by forming the contacts to allow the leads of a packaged semiconductor device to pass through the contacts. Both AC and DC testing may be done because the contact length is substantially shortened.

Wiping contacts

An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12) and a switch (18). The drive circuit (11, 41) may be a current mode drive circuit (11) or a voltage mode drive circuit (41). The drive circuit (11, 41) is coupled to the programmable measurement unit (12) and a device under test (64). In a DC mode of operation, the switch (18) is configured to couple a sense terminal (39) with one end of an isolation resistor (66). A second end of the isolation resistor (66) is connected to a pin (63) of the device under test (64). In an AC mode of operation, the switch (18) is configured to couple the sense terminal (39) with the drive circuit (11, 41) and the force terminal (35) of the programmable measurement unit (12).

Method for testing integrated devices

A cantilever spring (16) and a method for temporarily coupling a semiconductor package (36) to a transmission line (14) by means of the cantilever spring (16). The cantilever (16) has first and second pressure points (22, 32) that contact the transmission line (14). A force is applied to a third pressure point (32) which moves the first and second pressure points in opposite directions along the transmission line (14). In addition, the force on the third pressure point moves an end (21) of the cantilever spring (16) in a direction away from the transmission line (14). A lead (37) from the semiconductor package (36) contacts a portion of the end (21). Electrical signals are transmitted between the semiconductor package (36) and a tester via the cantilever spring (16) and the transmission line (14), wherein the electrical signals are for testing a semiconductor device (30).

Cantilever spring and method for temporarily coupling a semiconductor

Integrated circuit test with programmable source for both AC and DC

A test fixture operates under the control of a computer to make automatic correction in test contact spacing between the test fixture contact pins and the circuit under test. The computer detects continuity test failures and raises the test fixture to bring the test contact pins into proximity with the leads of the circuit under test. The computer controls rotation of a motor that drives a screw and moves a shaft and wedge assembly in the horizontal direction. A push rod is attached to the test fixture by way of a base plate and angle brackets. The push rod resting on the wedge slide up and down to raise and lower the test fixture.

Apparatus and method of correcting loss of test contact continuity

The present invention includes a method for transporting articles (24), and a pick and place apparatus (10) for implementing the method. The apparatus includes a suction tube (12) coupled to a pickup cam (11) and a pin (22) coupled to a hold-down cam (18). The pickup cam (11) and the hold-down cam (18) share a common cam shaft (15). In addition, the suction tube (12) is coupled to a pressure reduction apparatus (16) which is enabled throughout the transport process. The cam shaft (15) is rotated in a first direction to couple the article (24) to a suction cup (14). The article (24) is transported to a desired location and released by reversing the direction of rotation of the cam shaft (15). The article (24) is released by the pin (22) pushing the article (24) away from the suction cup (14).

Method and apparatus for picking and placing an article

A semiconductor probe card having a plurality of micromachined probes tips for contacting an array of electrode pads formed on a semiconductor integrated circuit is provided. The plurality of probe tips are formed on the top surface of the substrate wherein the probe tips are arranged in an array matching of electrode pads on the integrated circuit to be tested. A portion of the semiconductor substrate underneath the probe tips is thin, so that the probe tips rests on a flexible diaphragm or beam.

Micromachined semiconductor probe card

A handler (11) which transports a number of packaged semiconductor devices (12) in a boat (23) to a test head (14) and tests the devices (12) is provided. The handler (11) has an input staging section (29), a testing section (31) which is adjacent to the test head (14), and an output staging section (36). A boat transport (27a, 27b) moves the boat (23) from the input staging section (29) to the testing section (31) and from the testing section (31) to the output staging section (36). The boat transport (27a, 27b) operates during the device testing to provide substantially parallel operation of the testing and handling steps. A boat lift (39) moves the boat (23) to the test head (14) to allow the packaged semiconductor devices (12) to remain in the boat (23) during testing.

Packaged semiconductor device handler

An ECL logic circuit having differential inputs and differential outputs and programmable propagation delay time is provided. The differential inputs are coupled to a first differential amplifier as is done on a conventional differential ECL circuit. A second feedback differential amplifier is coupled to the collectors of the first differential amplifier. Current in the first differential amplifier is normally constant, whereas current in the feedback differential amplifier can be programmably adjusted. By adjusting the current in the feedback differential amplifier the feedback differential amplifier loads the logic circuit forcing a voltage swing which is up to double that normally provided by the first differential amplifier, therefore increasing the time required for either output to change from a logic LOW to a logic HIGH. This delay results in a variable propagation delay which is controlled by adjusting current flow in the feedback differential amplifier.

Programmable time delay circuit for digital logic circuits

An antimetastable state circuit which detects when a data edge is so close to a clock edge that it would result in a metastable state in a time measurement circuit is provided. When a potential metastable state is detected, the antimetastable circuit delays the data edge with respect to the clock edge by a known amount so as to avoid the metastable state. The delayed edge is used to start the time measurement circuit, and the next clock edge is used to stop the time measurement circuit. When the known delay has been added, it is subtracted from the measured time, to produce an accurate measurement of the elapsed time between the rise of the data edge and the rise of the clock edge.

Antimetastable state circuit

An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.

Method and apparatus for testing high pin count integrated circuits

An apparatus for use in high speed digital testing of high pin count logic circuits is provided wherein a plurality of terminal electronics units are connected in series to each other and to one channel of a multi-channel tester. Each pin electronics unit stores a test vector from the test channel in a first mode, and applies the test vector to the circuit under test at high speed in a second mode. Each pin electronics unit can also store response data from the circuit under test.

Method and apparatus for high speed integrated circuit testing

A digital time base generator circuit is provided having a first phase locked loop for multiplying a reference frequency by an integer amount and a second phase locked loop for multiplying the reference frequency by a different integer amount. The first and second multiplied reference frequencies are then divided back down to the original reference frequency by two dual modulus frequency dividers. In this manner a start signal and a stop signal are generated such that the frequency of the start and stop reference signals is the same as the original reference frequency and the time delay between an edge of the start signal and edge of the stop signal can be changed by altering the mode of either of the dual modulus frequency dividers.

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Gilbert, AZ, United States of America

Mavin C Swapp