Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Sip - Societa Italiana Per L'esercizio Delle Telecommunicazioni

Mauro Marchisio

Marco Gandini

Pierangelo Garino

Andrea Finotello

Giovanni Ghigo

Gianmario Bollano

Alessandro Torielli

Marco Mattavelli

Martin Gumm

Stephanie Dogimont

Didier Nicoulaz

Fabio Bellifemine

Giovanni Pucci

Frederich Mombers

Alfredo Rinaudo

Circuit for motion estimation in digitized video sequence encoders

An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

Device for manipulating compressed video sequences

The video control circuit is particularly adapted to multimedia applicati, wherein image transmission services are offered in addition to usual telephone speech and data transmission services. The circuit is capable of processing both photographic and graphic video images, satisfying both the relevant CCIR standards and the specifications proper to personal computers, VGA EGA, etc. so as to allow the representation of either types of images on an only type of display. To this end, it generates both timings proper to the CCIR standards, for a resolution of 720 columns per 480 lines, with an upper representation limit of graphic planes of 1024 columns per 1024 lines.

Video control circuit for multimedia applications with video signal

An electronic circuit for generating error detection codes in digital sigs organized into serial data blocks, which derives the error code from the coefficients of a remainder polynomial obtained from the division of a dividend polynomial, whose coefficients are the bits of each serial block, and a convenient divisor polynomial. The circuit has a shift register wherein at the beginning of each serial data block the reset and the first datum load are performed in a single clock interval.

Electronic circuit for generating error detection codes for digital

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Turin, Italy

Mauro Marchisio