Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Micron Technology Incorporated

Other

Stmicroelectrics S.r.l.

Mauro Luigi Sali

Simone Bartoli

Corrado Villa

Lorenzo Bedarida

Fabio Tassan Caser

Marcello Carrera

Antonio Russo

Marcello Cane

Marco Dallabora

Alessandro Magnavacca

Giuseppe Cariello

Ugo Russo

Antonino Pollio

Carla Maris Golla

Antonino Geraci

Andrea Pozzato

Giuseppe Vito Portacci

Andrea Vigilante

Gianluca Scalisi

Andrea Salvioni

Stefano Falduti

Antonino Mondello

Emanuele Confalonieri

Giorgio Servalli

Paolo Giuseppe Cappelletti

Emilio Camerlenghi

Carlo Lisi

Tecla Ghilardi

Francesco Mastroianni

Massimiliano Mollichelli

Claudio Nava

Vincenzo Dima

Antonio Geraci

Andrea Bellini

Francesco M Brani

Stefan Schippers

Elena Cussotto

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Memory system tester using test pad real time monitoring

Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.

Initialization techniques for memory devices

Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

Adjustable NAND write performance

A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.

Flash memory device with improved management of protection information

A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

Nonvolatile memory device with simultaneous read/write

An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read

An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method

A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.

Non-volatile memory device with burst mode reading and corresponding reading method

A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

Non-volatile memory with a charge pump with regulated voltage

An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration

A memory device comprises a plurality of independent memory sectors, external address signal inputs for receiving external address signals that address individual memory locations of the memory device, the external address signals including external memory sector address signals allowing for individually addressing each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. A first and a second alternative internal memory sector address signal paths are provided for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion. A programmable circuit activates either one or the other of the first and second internal memory sector address signal paths, so that a position of each memory sector in a space of values (00000h-3FFFFh) of the external address signals can be changed by activating either one or the other of the first and second internal memory sector address signal paths.

Sectored semiconductor memory device with configurable memory sector addresses

An architecture handles internal voltages in a non-volatile memory array which is split into at least first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of the internal voltages, which are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array; and a control system connected to the pluralities of generators to handle the correct activation of the different generators in the different conditions of the memory array operation.

Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory

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Sant'Angelo Lodigiano, Italy

Mauro Luigi Sali