Nxp B.v.

Maurits Storms

Roger Cuppens

Soenke Ostertun

Cas Groot

Frans J List

Frantisek Cevela

Rob Verhaar

Guido J M Dormans

Robert H Beurze

There is described a driver circuit () for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch () comprising a first latch input terminal (), a first latch control terminal (), a latch voltage supply terminal (), a first latch output terminal (), and a second latch output terminal (), wherein the level shifter latch () is adapted to provide, in dependency of a voltage at the first latch input terminal (), one of a first voltage and a second voltage at the first latch output terminal () and the other one of the first voltage and the second voltage at the second latch output terminal (), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal () and the second voltage is dependent on a voltage applied to the first latch control terminal (), (b) a first output stage () comprising a first switching element (N, N), a second switching element (N), a first voltage supply terminal (), a second voltage supply terminal (), and a first biasing voltage output terminal (), wherein the first switching element (N, N) is adapted to connect the first biasing voltage output terminal () to the first voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the second switching element (N) is adapted to connect the first biasing voltage output terminal () to the second voltage supply terminal () in dependency of the voltage at the second latch output terminal (), and (c) a second output stage () comprising a third switching element (N), a fourth switching element (N), a third voltage supply terminal (), a fourth voltage supply terminal (), and a second biasing voltage output terminal (), wherein the third switching element (N) is adapted to connect the second biasing voltage output terminal () to the third voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the fourth switching element (N) is adapted to connect the second biasing voltage output terminal () to the fourth voltage supply terminal () in dependency of the voltage at the second latch output terminal ().There is also described a memory system and a method of operating the driver circuit.

Driver circuit for memory devices

Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.

Method and system for fast initialization of a memory unit

Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

Flash- and ROM-memory

The memory circuit comprises at least one memory element (T), a sense amplifier (SA) for sensing a state of the memory element (T), a switching device (T) for selectively coupling the sense amplifier (SA) to the memory element (T), The sense amplifier (SA) comprises a first module (M) and a second module (M). The first module (M) provides a first current limited to a maximum value (Iref+Ibias). The second module (M) provides a second current which decreases from a value higher than the maximum value at the start of a sensing operation until a value lower than the maximum value at the end of the sensing operation. The memory circuit has a third module (CS) for sinking a third current (Ibias) at a side of the switching device (T) coupled to the memory element (T).

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Best, Netherlands

Maurits Storms