Nxp B.v.

Nxp Usa, Inc.

Maurits Mario Nicolaas Storms

Jon Scott Choy

Michiel Jos Van Duuren

Erik Maria Van Bussel

Karthik Ramanan

Ivan Jesus Rebollo Pimentel

Thomas Pichler

Jacob Williams

Padmaraj Sanjeevarao

Godefridus Adrianus Maria Hurkx

Timothy J Strauss

Jukka Riihiaho

Christopher N Hume

Timothy Strauss

Sergio Masferrer

Silvia Wagemans

Christopher Nelson Hume

Jacob T Williams

Jukka Sakari Riihiaho

Cas Groot

A non-volatile memory (NVM) includes a daisy chained normal read bus, a daisy chained verify read bus, and a plurality of partitions. Each partition includes a portion of the daisy chained normal read bus and a portion of the daisy chained verify read bus. A memory controller receives read data in response to normal read access requests to the NVM via the daisy chained normal read bus and, in response to write access requests to the NVM, receives verify read data via the daisy chained verify read bus. A bus sharing circuit is coupled between a first partition and a second partition. The bus sharing circuit, in response to a sharing control signal, selectively repurposes portions of the daisy chained verify read bus in at least one of the partitions to communicate read data to the memory controller in response to a normal read access request to the NVM.

Partitioned non-volatile memory (NVM) having a normal read bus and a verify read bus

A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Column repair in a memory system using a repair cache

A radio frequency identification (RFID) transponder includes a current control module for controlling a current consumption of a memory based on an amount of available power, and a control logic for controlling a memory operation in response to the control of the current consumption by the current control module. The RFID transponder further includes a power detector that is configured to continuously monitor and detect the amount of available power and output a power-dependent control signal. The power-dependent control signal is used by the RFID transponder to control the current consumption of the memory in dependence on the available power.

Agile time-continuous memory operation for a radio frequency identification transponder

A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Memory with one-time programmable (OTP) cells and reading operations thereof

Embodiments of a method for controlling a charge pump and a control device for a charge pump are described. In one embodiment, a method for controlling a charge pump involves monitoring a power-on status of the charge pump, calculating a duty cycle of the charge pump within a time period based on the power-on status of the charge pump, and adjusting at least one of a clock frequency setting and a capacitance setting of the charge pump in based on the duty cycle of the charge pump. Other embodiments are also described.

Method and system for controlling a charge pump

Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described.

2T and flash memory array

A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.

Phase change memory (PCM) architecture and a method for writing into PCM architecture

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Best, Netherlands

Maurits Mario Nicolaas Storms