Kepler Computing Inc.

Mauricio Manfrini

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Noriyuki Sato

Somilkumar J Rathi

Niloy Mukherjee

Tanay Gosavi

Rafael Rios

Ramamoorthy Ramesh

Pratyush Pandey

Jason Y Wu

Gabriel Antonio Paulius Velarde

Zeying Ren

Fnu Atiquzzaman

James David Clarkson

Abel Fernandez

Debo Olaosebikan

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Methods of fabricating planar capacitors on a shared plate electrode

Capacitor devices with shared electrode and methods of fabrication

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

Integration of 2T-C for memory and logic applications

Planar capacitors with shared electrode and methods of fabrication

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Capacitor integrated with a transistor for logic and memory applications

Trench capacitors with shared electrode

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices

A method to deposit a multi-layer stack for device applications includes implementing a model driven target selection for deposition. One or more targets may be procured with an initial stoichiometric composition or elemental purity. The targets may be utilized to form the multi-layer stack, and measurements may be made of chemical composition and electrical properties of the multi-layer stack. The measurements may be compared to reference target values and if measurement results are not within tolerance, the composition of the targets can be changed to yield a successive multi-layer stack. The process can be iterated until measurement results are within tolerance of target results. Additional experimentation with post deposition thermal anneal can be performed to optimize multi-layer stack properties.

Iterative method of multilayer stack development for device applications

A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Multi-level hydrogen barrier layers for memory applications and methods of fabrication

Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies

Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies

Dual hydrogen barrier layer for memory devices

Integrated trench and via electrode for memory device applications and methods of fabrication

Growing community of inventors

Heverlee, Belgium

Mauricio Manfrini