International Business Machines Corporation

Maurice T McMahon

Henri D Schnurmann

Prabhakar Goel

Arthur R Zingher

Perwaiz Nihal

Burhan Ozmat

Scott L Jacobs

Edward P Hsieh

A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.

Diagnostics of a board containing a plurality of hybrid electronic

A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a 'good machine' simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

Method of partitioning, testing and diagnosing a VLSI multichip package

The disclosure is directed to an electronically selectable redundant array or memory technique and circuitry. More particularly the invention utilizes Level Sensitive Scan Design (LSSD) circuitry with limited modification to perform the additional function of selecting a redundant word (or words) in a memory chip containing at least one defective word. The correction mechanism is independent of which word line (or word lines) is bad, and is therefore independent of I/O pin (or pad) connection of the array chip.

Electronically selectable redundant array (ESRA)

Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be 'isolated' for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the 'Level Sensitive Scan Design' (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.

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Poughkeepsie, NY, United States of America

Maurice T McMahon