Stmicroelectronics (crolles 2) Sas

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Clariant (france) Sa

Stmicroelectronics S.a.

Other

Commissariat a L'energie Atomique

Az Electronic Materials USA Corp.

France Telecom

Clariant Chimie S.a.

France Telecom (etablissement Public National)

Stmicroelectronics (rousset) Sas

Maurice Rivoire

Eric Jacquinot

Pascal Letourneau

Guillaume Bouche

Fabrice Casset

Daniel Bensahel

Yves Campidelli

Caroline Hernandez

Lea Di Cioccio

Léa Di Cioccio

Pierric Gueguen

Jean-Christophe Coiffic

Viorel Balan

Danielle Thomas

Fabrice Cassett

Catherine Euvrard

A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.

Plurality of substrates bonded by direct bonding of copper recesses

A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.

Method for modifying the crystalline structure of a copper element

A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.

Method of planarizing recesses filled with copper

A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.

Simplified copper-copper bonding

A surface of a substrate comprising microcavities leading out of the substrate is placed in contact with an aqueous solution comprising a plurality of suspended particles and a fabric. Perpendicular pressure is applied the expanse of the substrate between the fabric and the surface of the substrate, and relative movement of the fabric and the surface is applied to the expanse of the substrate. At least one particle is thus fed into each microcavity, therein forming a porous material that is a catalyst material for nanothread or nanotube growth.

Method for forming porous material in microcavity or micropassage by mechanicochemical polishing

A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.

Method for producing a membrane comprising micropassages made from porous material by chemical mechanical polishing

A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.

Light sensor located above an integrated circuit

Abrasive composition for the integrated circuits electronics industry comprising an aqueous acid suspension of individualized colloidal silica particles not linked to each other by siloxane bonds and an abrasive surfactant, this abrasive being for mechanical chemical polishing in the integrated circuits industry, comprising a fabric impregnated by such a composition, and a process for mechanical chemical polishing.

Abrasive composition for the integrated circuit electronics industry

A method of making a variable capacitor by forming a grove portion in an insulating substrate, two upper portions of the substrate located on either side of the groove portion forming two lateral edges, a conductive layer covering the inside of the groove portion, a flexible conductive membrane, placed above the groove portion by bearing on the edges, a dielectric layer covering the conductive layer or the membrane to insulate the conductive layer and the membrane, and terminals of application of a voltage between the conductive layer and the membrane, and such that the depth of the groove portion continuously increases from one of the edges to the bottom of the groove portion, and that the conductive layer covers the inside of the groove portion at least to reach one of the two edges, that it may cover.

Method of making a variable capacitor component

Abrasive composition for the integrated circuits electronics industry

The process consists in depositing, by chemical vapour deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450&deg; C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.

Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively, and multilayer products obtained

Process for fabricating a planar heterostructure

Process for mechanical chemical polishing of a layer of an aluminium or aluminium alloy conducting material used in the microelectronics semi-conductors industry in which said aluminium or aluminium alloy layer is abraded using an abrasive composition which comprises an alkaline aqueous suspension of individualized colloidal silica particles not linked to each other by siloxane bonds, a tetraalkylammonium hydroxide and an oxidizing agent.

Process for mechanical chemical polishing of layer of aluminium or aluminium alloy conducting material

A composition for mechanical chemical polishing of a layer in an insulating material based on a polymer with a low dielectric constant, comprising an acid aqueous suspension of cationized colloidal silica containing individualized colloidal silica particles not linked to each other by siloxane bonds and water as the suspension medium, process for mechanical chemical polishing of a layer of insulating material based on a polymer with a low dielectric constant and abrasive for the mechanical chemical polishing of a layer of insulating material based on a polymer with a low dielectric constant.

Growing community of inventors

Meylan, France

Maurice Rivoire