Ncr Corporation

Symbios, Inc.

Lsi Logic Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Maurice M Moll

Daniel L Ellsworth

Harold S Crafts

Gayle W Miller

John D Walker

Nicholas J Szluk

Hoang P Nguyen

Werner A Metz, Jr

Scott H Cravens

This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.

Antifuse device for use on a field programmable interconnect chip

An integrated circuit formed on a semiconductor substrate has a contact pad for communicating signals between an external device and an internal signal line. The pad is protected by an SCR that conducts electrostatic discharge pulses from the pad directly to a current sink. The SCR includes a subregion underneath a field oxide that has a field inplant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that SCR triggers before an ESD pulse can cause latch-up or damage in other devices in the integrated circuit.

Field implant for silicon controlled rectifier

A low current output driver for a gate array. The driver has first and second reference voltage sources, a first transistor of a first conductivity type, and a plurality of second transistors of a second conductivity type. The first transistor is connected between the first reference voltage source and the output. The second transistors are series connected between the first and second reference voltage sources. The control electrode of the first transistor is connected to a common point between two of the second transistors. At least one of the second transistors is diode connected to provide an intermediate voltage to the control electrode of the first transistor, thereby reducing the output current flow.

Low current driver for gate array

An output driver for reducing current spikes in an output comprising three transistors connected between an output node and a reference voltage terminal. The first transistor is responsive to an input data signal, the second transistor is responsive to a first feedback signal from the output, and the third transistor is responsive to a second feedback signal from the output.

Current limiting output driver

An integrated circuit two transistor full wave rectifier suitable for fabrication in a CMOS, NMOS or PMOS process and characterized by a high level of integration based upon shared utilization of doped regions. In one form, the full wave rectifier is configured from two diode connected field effect transistors and two parasitic p-n junctions, all formed in a substrate region of common impurity type.

Two transistor full wave rectifier

A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface. Following the etch of the deposited dielectric to the level of the plateau and active region surfaces, a second mask, defined to be slightly larger than the active regions, is formed over the substrate. A selective etch is then applied to remove the plateau regions and thereby form new trenches approximating in depth the first trenches. A second conformal deposition of dielectric follows, to fill the plateau region defined trenches in the manner of the first dielectric deposition. An etch of the second dielectric to the surface of the active regions follows to complete the fabrication. The substrate surface is planar and now divided into active regions which are separated by oxide filled, arbitrary width trenches.

Two mask technique for planarized trench oxide isolation of integrated

In a one time programmable memory device having a memory cell, a programmable device in the memory cell having a high initial resistance, a user readable circuit for reading the condition of the programmable device, and capacitance coupled with the initial resistance and having an RC time constant therewith, a circuit and its method for non-destructively testing the programmability of the programmable device. A switch device is included in the user readable circuit and is connected to the capacitance. The switch device has a first condition for discharging the capacitance and a second condition for allowing the capacitance to charge through the programmable device. An output circuit in the user readable circuit indicates when the charge on the capacitance reaches a predetermined threshold. A test enabling element is responsive to a test enable signal for selectively changing the switch device between its second condition and its first condition to conduct a test for measuring the RC time constant, thereby testing the programmability of the programmable device.

Non-destructive method and circuit to determine the programmability of a

An electrically programmable memory cell using selectively deposited tungsten on a sidewall to define a fuse region. Fabrication of the fuse structure involves only a single mask departure from standard MOSFET processing during which a selective isotropic etch of a silicon nitride sidewall structure facilitates the formation of a fuse structure comprised of a tungsten layer selectively deposited on exposed silicon and a source/drain diffusion separated by an oxide or selectively thinned oxide as the degenerating element. The actuation region of the fuse is proportional to the thickness of the selectively deposited tungsten layer.

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Fort Collins, CO, United States of America

Maurice M Moll