France Telecom Establissement Autonome De Droit Public

Maurice Bonis

A process for fabricating a semiconductor device using local silicide interconnection lines make it possible to fabricate an integrated circuit having a plurality of electronic elements disposed on a semi-conductor substrate. The electronic elements are formed on the substrate such that they are grouped into a first region and a second region adjacent to the first region, each of these regions having predetermined conductivities. The first region has a layer of dielectric material disposed upon it with at least one capacitive element disposed on the dielectric layer. The capacitive element includes a first electrode layer and a second electrode layer. The second region has at least one double junction metal-insulator semi-conductor field effect transistor (MISFET) located therein. The MISFET includes at least three regions, a gate region and two active regions, a source region and a drain region. In accordance with the teachings of the present invention, a process is provided whereby one of said two active regions is electrically connected by a first local connection line to the first electrode layer of the capacitive element, a bond pad is disposed on the gate region, a source bond pad is disposed on the source region, a drain bond pad is disposed upon a drain region and a second electrode layer of the capacitive element, simultaneously, in the same formation step. This is advantageously accomplished inter alia by depositing and then etching the silicide of a refractory metal.

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Crolles, France

Maurice Bonis