Varian Semiconductor Equipment Associates, Inc.

Maureen Petterson

John J Hautala

Tristan Yonghui Ma

Anthony Renau

Costel Biloiu

Alexandre Likhanskii

Christopher A Rowland

Ludovic Godet

Steven Robert Sherman

Kevin R Anglin

Boya Cui

A workpiece processing apparatus allowing independent control of the voltage applied to the shield ring and the workpiece is disclosed. The workpiece processing apparatus includes a platen. The platen includes a dielectric material on which a workpiece is disposed. A bias electrode is disposed beneath the dielectric material. A shield ring, which is constructed from a metal, ceramic, semiconductor or dielectric material, is arranged around the perimeter of the workpiece. A ring electrode is disposed beneath the shield ring. The ring electrode and the bias electrode may be separately powered. This allows the surface voltage of the shield ring to match that of the workpiece, which causes the plasma sheath to be flat. Additionally, the voltage applied to the shield ring may be made different from that of the workpiece to compensate for mismatches in geometries. This improves uniformity of incident angles along the outer edge of the workpiece.

Extreme edge uniformity control

A method includes providing a substrate, where the substrate has a patterned substrate surface, wherein the patterned substrate surface comprises a first surface region and a second surface region. The method may also include directing a depositing species to the patterned substrate surface; and directing angled ions to the patterned substrate surface, wherein the depositing species forms a deposit on the first surface region and does not form a deposit on the second surface region.

Techniques for selective deposition using angled ions

A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200&#xb0; C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200&#xb0; C. or greater.

Multiple patterning approach using ion implantation

Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.

Ion-assisted deposition and implantation of photoresist to improve line edge roughness

Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved.

Ion implantation for improved contact hole critical dimension uniformity

Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of patterning features atop a layer of a semiconductor device, and implanting ions into a sidewall surface of the set of patterning features. The method includes implanting ions at an angle nonparallel with the sidewall surface, for example, approximately 60&#xb0; to a plane normal to the sidewall surface. The method further includes etching the semiconductor device after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation as a pretreatment prior to etching, photoresist roughness is minimized, and sidewall striation and etch-induced line edge roughness is reduced. Approaches herein may also improve etch selectivity with respect to underlying layers disposed under the photoresist, as well as improved photoresist profiles.

Ion implantation for improved etch performance

A method for processing a substrate may include providing a patterning feature on the substrate, the patterning feature having a sidewall. The method may further include implanting a first ion species into the patterning feature during a first exposure, the first ion species having a first implantation depth; and implanting a second ion species into the patterning feature during a second exposure, the second ion species having a second implantation depth less than the first implantation depth.

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Salem, MA, United States of America

Maureen Petterson