Texas Instruments Corporation

Maureen A Hanratty

Wei William Lee

Amitava Chatterjee

Iqbal Ali

Greg A Hames

Qizhi He

Quzhi He

Rick L Wise

Francis Gabriel Celii

Katherine E Violette

Daty Michael Rogers

The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Antireflective structure and method

A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Transistor having improved gate structure

A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.

Process for monitoring the thickness of layers in a microelectronic device

A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer ( ) may be formed adjacent a substrate ( ). A disposable gate ( ) may be formed adjacent the primary insulation layer ( ). An isolation dielectric layer ( ) may be formed adjacent the primary insulation layer ( ). The disposable gate ( ) may be removed to expose a portion of the primary insulation layer ( ). The exposed portion of the primary insulation layer ( ) may be removed to expose a portion of the substrate ( ). The primary insulation layer ( ) may be selectively removable relative to the isolation dielectric layer ( ). A gate insulator ( ) may be formed on the exposed portion of the substrate ( ). A gate ( ) may be formed adjacent the gate insulator ( ).

Transistor having an improved gate structure and method of construction

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (,) having a channel region (,). A gate insulation (,) may be adjacent the channel region (,) of the semiconductor substrate (,). A gate (,) may be formed adjacent the gate insulation (,). A sidewall insulation body (,) may be formed adjacent a portion of the gate (,). The sidewall insulation body (,) is comprised of a silicon oxynitride material. An epitaxial layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the semiconductor substrate (,) substantially outward of the channel region (,). A buffer layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the epitaxial layer (,).

Transistor having an improved sidewall gate structure and method of construction

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

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Dallas, TX, United States of America

Maureen A Hanratty