Taiwan Semiconductor Manufacturing Comp. Ltd.

Faraday Technology Corporation

Mediatek Corporation

Mau-Lin Wu

Ming-Dou Ker

Wei-Jen Chen

Ju-Ya Chen

Chiou-Wei Tsai

Ho-Chi Huang

Guo-Hau Gau

Jian-Hsing Lee

Yi-Hsun Wu

Hung Der Su

Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.

Non-orthogonal multiple access wireless communications methods and apparatus thereof

A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.

Duplicate detection circuit for receiver

A fast Walsh transform (FWT) demodulator and a method are provided. The FWT demodulator includes a FWT correlator for receiving and transforming a first information based on a FWT method to output third information; power approximation devices (PAD) for receiving and calculating one of the third information to output an approximating power value respectively. Wherein, the approximating power values are divided into subgroups. A first unit of comparators selects subgroup-max-values from each subgroup. A plurality of power calculation devices (PCD) are for receiving and calculating one of the subgroup-max-value to output a precise power value respectively. A second unit of comparators is for selecting max power value from each precise power value to output a second information. By applying 'PAD' to replace 'PCD' into &#x201c;pre-selection&#x201d; subgroups with &#x201c;max-and-zero&#x201d; property, the invention can reduce the implementation cost without performance degradation.

Fast Walsh transform (FWT) demodulator and method thereof

Counting circuits applied to distance estimation for ultra wideband (UWB) application, in which a first counting unit generates a sequence of pseudo-random number series not including zero, a first recoding unit records a first series and a second series from the sequence according to a first signal and a second signal, and a transfer unit generates a binary counting value according to the first series and second series from the recording unit.

Counter circuits and distance estimation methods

A new ESD (Electrostatic Discharge) protection circuit with well-triggered PMOS is provided for application in power-rail ESD protection. A PMOS device is connected between the VDD and VSS power lines to sustain the ESD overstress current during the time that the ESD voltage is applied between the VDD and the VSS power lines. In deep submicron CMOS p-substrate technology, the weak point of ESD overstress control is typically associated with the NMOS device. For this reason, the invention uses a power-rail ESD clamp circuit that incorporates a PMOS device. Applying gate-coupled and N-well triggering techniques, the PMOS can be turned on more efficiently when the ESD overstress is present between the power lines. For p-substrate CMOS technology, it is difficult to couple a high voltage to the substrate of the NMOS device while high voltage is readily coupled to the N-well of a PMOS device. The proposed ESD clamp circuit can be applied efficiently to protect the ESD overstress between power rails.

Power-rail ESD clamp circuits with well-triggered PMOS

A layout form ESD-protection MOS transistors include gate electrodes of the ESD-protection MOS transistors being formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. The ESD protection transistors are NMOS and PMOS. The source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes. The wider ends of the gate electrodes straddle the peripheral boundaries of the active region. A modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner transistors.

Device layout to improve ESD robustness in deep submicron CMOS technology

An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Growing community of inventors

Hsinchu, Taiwan

Mau-Lin Wu