Telefonaktiebolaget Lm Ericsson (publ)

Mattias Palm

Lars Sundström

Daniele Mastantuono

Roland Strandberg

Sven Erik Mattisson

Henrik Sjöland

Fredrik Tillman

Ola Andersson

Christer Jansson

Martin Anderson

Pietro Andreani

Hanie Ghaedrahmati

In a pipelined Successive Approximation Register Analog to Digital Converter, SAR ADC, a Process, Temperature, and Voltage (PVT)-dependent bias voltage is generated and used to bias the inputs of comparators in at least the first SAR stage and residual amplifier (RA). This achieves a stable biasing and an operating point of the comparators and RA input stages that is independent of PVT variations, by tracking PVT variations in such a way that variations in MOS threshold voltage and drain-source voltage are counteracted. Additionally, a threshold common mode voltage is generated from the PVT-dependent voltage, which controls the amplification duration of the RAs such that the final RA output common mode voltage is substantially equal to the PVT-dependent voltage, which is used to bias the inputs of successive SAR stages. The threshold is set to account for logic delays in terminating the amplification based on the threshold comparison, to achieve the desired common mode amplifier output. The dependency on PVT of the threshold additionally cancels temperature variation from a differential stage transconductance of the RA. Further temperature stabilization is achieved by boosting the charge output by the RA to a capacitive load during part of the amplification.

PVT stabilization of pipelined SAR ADC

A successive approximation register analog-to-digital converter (SAR ADC) is disclosed, which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC comprises a capacitor bank for successively providing a plurality of signal levels based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC comprises controlling circuitry configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal. In some embodiments, a respective selector of each capacitor of the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or the sample value of an opposed version of the analog input signal. The setting of the respective selectors corresponds to a digital representation of a scaling value (e.g., a sample value of an oscillator signal) for the dynamically scaled version of the sample value of the analog input signal. Corresponding method, receiver, and wireless communication device are also disclosed.

Successive approximation register analog-to-digital converter

An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.

Time-interleaved analog-to-digital converter

A TI-ADC () comprising a group of sub-ADCs (A-A) is disclosed. During operation, M&#x2265;2 of the sub-ADCs (A-A) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC () from an analog to a digital representation. The total number of sub-ADCs (A-A) in the group is M+N, N&#x2265;1. The TI-ADC () comprises error-estimation circuitry () for estimating errors of the sub-ADCs (A-A). Furthermore, the TI-ADC () comprises a control circuit () configured to, for each input signal sample, assign which sub-ADC (A-A) is to operate on that input signal sample. The control circuit () is configured to, for sub-ADCs (A) in a first subset of the group of sub-ADCs (A-A), which are subject to error estimation by the error-estimation circuitry (), perform the assignment according to a first scheme. Moreover, the control N circuit () is configured to, for sub-ADCs (A) in a second subset of the group of sub-ADCs (A-A), which are not subject to error estimation by the error-estimation circuitry (), perform the assignment according to a second scheme, different from the first scheme.

Sub-ADC assignment in TI-ADC

A reference analog-to-digital converter (ADC) samples an input signal in parallel with sub-converters of a time-interleaved ADC. For each sub converter and for each of a plurality of output samples from the sub-converter, a calibration circuit determines whether the output sample from the sub-converter indicates an input signal polarity opposite that indicated by the reference ADC. For each such instance, a DC-offset sample is calculated as a difference between the output sample from the sub-converter and a target zero-crossing value for the sub-converter output. For each sub-converter, a series of DC-offset samples is filtered, to produce an average zero-crossing error for each sub-converter. This filtering may comprise a simple average, for example, or a moving average, a decaying filter, etc. Finally, a zero-crossing correction is applied for each of one or more of the sub-converters, based on the respective average zero-crossing error.

Calibration technique for time-interleaved analog-to-digital converters

An analog-to-digital conversion circuit () is disclosed. It comprises a switched-capacitor SAR-ADC, () arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC () is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator () arranged to supply the clock signal to the SAR-ADC (), and a post-processing unit () adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC ().

Leakage compensation for a successive approximation analog-to-digital converter

Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network. Moreover, the first capacitor network comprises a second set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the second set is connected to the second node and the second terminal of each capacitor in the first set is connected to the switch network. The SAR ADC further comprises a second capacitor network configured to control a gain of the SAR ADC.

Successive-approximation analog-to-digital converter

A pipelined ADC includes a first sub ADC and a second sub ADC. The second sub ADC is configured to receive, as an input, an analog residue generated by the first sub ADC. The first sub ADC is configured to operate in a first conversion phase, generating a digital output of the first sub ADC, and a second conversion phase, generating the analog residue. The first sub ADC includes a reference-voltage generator circuit configured to generate a reference voltage of the first sub ADC and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage is less than in the first mode of operation. The reference-voltage generator circuit is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.

Pipelined analog-to-digital converter

A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter () to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (); a digital-to-analog converter () to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators () in series, each having a feedback path comprising the analog-to-digital converter () in cascade with a digital-to-analog converter (), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.

Frequency selective circuit configured to convert an analog input signal to a digital output signal

In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.

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Bara, Sweden

Mattias Palm