Telefonaktiebolaget Lm Ericsson (Publ)

Mattias Hansson

Joakim Persson

Ben J Smeets

The present invention includes a method and device for calculating an encryption key, K', for use in the initialization of an encryption algorithm. The present invention discloses a method for calculating the encryption key, K&#x2032;(x), by obtaining a ciphering key, K(x), determining a maximum ciphering key length, L, based on the requirements of the two devices wishing to communicate, and determining a maximum usable encryption key length, L. The ciphering key, K(x), is then manipulated through an addition function or an exclusively-or function with a polynomial g(x). The result is multiplied with a polynomial g(x), which spreads the starting points of said encryption key, K&#x2032;(x). The encryption key is thus determined according to K&#x2032;(x)=g(x)[K(x) mod g(x)]. The method of calculating the encryption key, K&#x2032;, ensures that a maximum ciphering key length is not exceeded. In addition, the method provides new possible starting points each time a new encryption key, K&#x2032;, is generated.

Method and device for effective key length control

A low power linear feedback shift register includes an ordered set of register steps including memory devices. Enabling devices enable a single current memory device at every shift operation. Each register step includes a lower power memory device consuming a minimum amount of power when disabled, and a feedback device, an output terminal thereof being connected to an input terminal of the memory device, the feedback device having first and second input terminals connected to an output terminal of the memory device and an output terminal of a second subsequent memory device, respectively, in the set. The output terminal of each memory device is connected to a selection device, selecting at every shift operation the output terminal of a first subsequent memory device following the current memory device being enabled at the current shift operation.

Low power linear feedback shift registers

A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks include memory devices consuming a minimum of power when they are disabled and activated only when the value of the respective data output connection has to be changed.

Growing community of inventors

Lund, Sweden

Mattias Hansson