Micron Technology Incorporated

Aptina Imaging Corporation

Semiconductor Components Industries, LLC

Intel Ndtm US LLC

Mattia Cichocki

Violante Moschiano

Tommaso Vali

Umberto Siciliani

Maria-Luisa Gallese

Michele Incarnati

Andrea D'Alessandro

Federica Paolini

Brian A Vaartstra

Ulrich C Boettiger

Richard M Fastow

Chang Wan Ha

Loriston Ford

Jeffrey Mackey

Mitchell J Mooney

Guido Luciano Rizzo

Rick Holscher

Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device

Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

Pre-compensation of memory threshold voltage

Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.

Memory devices for reading memory cells of different memory planes

In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.

Concurrently reading first and second pages of memory cells having different page addresses

Pixel arrays are provided for image sensors that have barriers between color filters in an array of color filters. Color filter barriers may be formed from a transparent or semi-transparent material. Color filter barriers may be formed from a low refractive index material. Color filters may be etched and color filter barrier material may be formed in the etched regions of the color filters. If desired, a layer of color filter barrier material may be etched to form open regions and color filter material may be formed in the open regions of the color filter barrier material. An image sensor may be a front-side illuminated image sensor or a back-side illuminated image sensor.

Dielectric barriers for pixel arrays

A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.

Process for wet passivation of bond pads for protection against subsequent TMAH-based processing

Protective layer for bond pads

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Rome, Italy

Mattia Cichocki