Nordic Semiconductor Asa

Matti Tiikkainen

Marko Winblad

James Nevala

Markku Vähätaini

Hannu Talvitie

Veli-Pekka Junttila

Harri Matomäki

A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.

Memory-efficient hardware cryptographic engine

A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.

Hardware accelerator for Feistel block ciphers

An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Direct memory access controller

A hardware cipher engine encrypts or decrypts a block of input data from a sequence of blocks using a cipher operation where the block of output data depends on the input block's position in the sequence. In a random-access mode of operation, the engine receives a sequence position, receives a block of input data having that position, and outputs a block of output data without outputting data that encrypts, or that decrypts, every block of input data preceding the received position. In some embodiments, the operation is a stream cipher, and the engine generates a sequence of keystream blocks and performs a combining operation between the input block and a keystream block having a corresponding sequence position. In other embodiments, the cipher operation is a block cipher, and the engine generates, but doesn't output, blocks of data that encrypt, or decrypt, one or more blocks preceding the received input block.

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Trondheim, Norway

Matti Tiikkainen