Memory Technologies LLC

Nokia Corporation

Nokia Mobile Phones Limited

Spyder Navigations LLC

Matti Kalevi Floman

Kimmo Juhani Mylly

Jani Klint

Jukka-Pekka Vihmalo

Janne Tapani Nurminen

Jani Hyvonen

Markku Lipponen

Tapio Hill

Jani J Klint

Ari Aho

Jani Hyvönen

Sakari Sippola

Mikko Siltanen

A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described.

Apparatus and method to provide cache move with non-volatile mass memory system

The invention relates to a method comprising measuring the temperature of at least one location of a non-volatile memory; determining if said temperature measurement indicates that the data retention time of data stored at said at least one location is reduced below a threshold; and re-writing said data to said non-volatile memory in a response to a positive determination.

Method and device for temperature-based data refresh in non-volatile memories

Examples of enabling cache read optimization for mobile memory devices are described. One or more access commands may be received, from a host, at a memory device. The one or more access commands may instruct the memory device to access at least two data blocks. The memory device may generate pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks.

Mobile memory cache read optimization

A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device).

Virtual memory module

A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.

User selectable balance between density and reliability

The invention relates to a method comprising measuring the temperature of at least one location of a non-volatile memory; determining if said temperature measurement indicates that the data retention time of data stored at said at least one location is reduced below a threshold; and re-writing said data to said non-volatile memory in response to a positive determination.

Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Method, an interface for volatile and non-volatile memory devices as well as a related computer program product, and a device

A method for enabling cache read optimization for mobile memory devices is described. The method includes receiving one or more access commands, at a memory device from a host, the one or more access commands instructing the memory device to access at least two data blocks. The at least two data blocks are accessed. The method includes generating, by the memory device, pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks. Apparatus and computer readable media are also described.

Accessing data blocks with pre-fetch information

A method for monitoring the status of a memory device is disclosed. The method includes, during operation of the memory device, exercising a first portion of the memory device more than at least one other portion of the memory device in order to induce an accelerated rate of aging of the first portion. The first portion is monitored to detect at least a potential for a failure in the first portion. According to the method, in response to monitoring the first portion, at least one corrective action is performed. Apparatus and computer readable media are also disclosed.

Providing protection for a memory device

A host device is coupled to a peripheral device such as a multi media card or the like, where the peripheral device includes a solid state data storage segment. The peripheral device has means for initiating a defragmentation function, such as registers for comparing a current performance measure against a threshold performance metric, or block validity parameters received form the host device for the data storage segment of the peripheral device. Once met, the means for initiating cause a defragmentation function to execute on the data storage segment. A logical layer of the data storage segment is accessed by the host device and a physical layer of the data storage segment is accessed by the peripheral device. The defragmentation program may be resident on either the host or peripheral device. Defragmentation may be enabled to execute automatically once initiated, such as by a continuous or periodic background scan of current performance of the data storage segment.

Growing community of inventors

Kangasala, Finland

Matti Kalevi Floman