Nxp Usa, Inc.

Nxp B.v.

Matthis Bouchayer

Cristian Pavao Moreira

Jean-Stephane Vigier

Pierre Pascal Savary

Birama Goumballa

Dominique Delbecq

Andres Barrilado Gonzalez

A radar device () is described that includes at least one transceiver () configured to support frequency modulated continuous wave (FMCW); radar device () and a digital controller (). A temperature sensor system includes a plurality of temperature sensors () coupled to one or more circuits () in the at least one transceiver (). The digital controller () comprises or is operably coupled to an over-temperature emulation circuit () configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal () into the temperature sensor system ().

Temperature sensor system, radar device and method therefor

A radar device () is described that includes at least one transceiver () configured to support frequency modulated continuous wave (FMCW); a digital controller (); and a temperature sensor system comprising a plurality of temperature sensors () coupled to various circuits () in the at least one transceiver (). The digital controller () of the radar device () is configured to monitor a temperature of the various circuits () by polling temperature values of the plurality of temperature sensors ().

Temperature sensor system, radar device and method

An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.

Duty cycle monitor circuit and method for duty cycle monitoring

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit () configured to: receive a modulated embedded master-slave clock signal () that comprises a system clock signal () with an embedded frame start signal (); demodulate the modulated embedded master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit, integrated circuit and method for clock distribution and synchronization

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit () coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (); and transmit the modulated embedded master-slave clock signal () to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device () and at least one slave device ().

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Toulouse, France

Matthis Bouchayer