Xilinx, Inc.

Matthieu P H Cossoul

Shekhar Bapat

Madabhushi V R Chari

Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S' is first provided close to node S that generates signal patterns to route through a path N&#x2032; to load L. When it is impractical to test a network path N from source to load L, a load L&#x2032; is further provided close to load L that receives the signal patterns from a routing path N&#x2033; provided from source S. The paths N&#x2032; and N&#x2033; overlap to cover all the routing resources of the path N.

Method to test routed networks

A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.

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Sunnyvale, CA, United States of America

Matthieu P H Cossoul