Infineon Technologies Ag

Matthias Von Daak

Peter Ossimitz

Gottfried Beer

Thomas Kern

Dirk Hesidenz

Esther Vega Ordonez

Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Method for manufacturing a semiconductor chip with each contact pad having a pad cell associated therewith

A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Method of manufacturing and testing a chip package

The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line ( ) being assessed, the evaluation circuit ( ) comprising a bit line decoder ( ) and a precharge and converter circuit ( ). In order to reduce the read-out duration particularly in the case of large scale integrated memory cells ( ), a current source ( ) is provided, which increases the read-out current (I ) by an offset current (I ).

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Markt Schwaben, Germany

Matthias Von Daak