Micronas Gmbh

Trident Microsystems (far East) Ltd.

Other

Entropic Communications, Inc.

Trident Microsystems, Inc.

Matthias Vierthaler

Carsten Noeske

Thomas Hilpert

Dieter Luecking

Florian Pfister

Martin Winterer

Stefan Mueller

Herbert Alrutz

Dieter Lücking

Methods and systems are provided for noise suppression in data, particularly data comprising video and/or audio data. An input adjustment, based on a corresponding input adjustment value, may be applied to received input data that comprises video and/or audio data; and an output adjustment, based on a corresponding output adjustment value, may be applied to output data corresponding to previously processed received input data. The input adjustment value may be re-calculated based on an outcome of applying the input adjustment to the received data, and when a change occurs in the input adjustment value the change in the input adjustment value may be applied to subsequent received input data, and at the same time, and based on the change in the input adjustment value, a corresponding change may be applied at least some of data corresponding to previously processed received input data.

Method and device for noise suppression in a data processing arrangement

A method and device for noise suppression in a data processing device may have input data entered into a storage device and saved as storage data, the storage data may be processed by a data processor and may be output as output data from the storage device. The input data may be scaled with an input scaling value from a scaling device, and the output data may be scaled with an output scaling value from the scaling device. When the input scaling value may be altered, the storage data may also be altered for noise suppression. The storage device and/or the scaling device may be configured and/or actuated such that the storage data may be changed in accordance with a change in the input scaling value. Some or all of the storage data may be changed in accordance with a change in the input scaling value, and upon a change in the input scaling value by a change value the storage data may also be changed with the same change value. Upon a change in the input scaling value, the output scaling value may be changed, and upon a change in the input scaling value by the change value, the output scaling value may be changed by the same change value. The output scaling value may be the inverse of the input scaling value, and the input scaling value may be changed if a value of the input data goes above or below a threshold value. The input scaling value may also be changed if a predetermined number of the input data values of the input data and/or the input data values for a predetermined duration go above or below a threshold value (e.g., in averaged or weighted manner). Upon going above the threshold value, the input scaling value may be set at a predetermined value. Upon going above or below the threshold value, the input scaling value may be changed by a scaling step value as the change value. A change in the storage data may occur at the same time as a change in the input scaling value, and a change in the output scaling value may occur at the same time as a change in the input scaling value.

Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t&#x2261;[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Memory access control in a multiprocessor system

An audio processing system includes a speech detector that receives and processes an audio input signal to determine if the input signal includes components indicative of speech, and provides a control signal indicative of whether or not the audio input signal includes speech. A speech processing device receives the audio input signal and processes the audio input signal to improve its quality if the control signal indicates that the audio input signal includes speech.

Circuit arrangement and method for detecting and improving a speech component in an audio signal

A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to be stored in the data memory arrangement, and an address memory arrangement to store access addresses. The access addresses are logically linked to the given data type of the data, and/or a distribution of the data to the arithmetic/logic units is dependent on the access addresses, and/or a storage of the output data as the data is dependent on the access addresses.

Processor for processing data using access addresses linked to the data type of the processed data

The speech intelligibility of an audio signal of unchanged volume is improved by raising the total audio signal by a constant factor and lowering the amplitude of this raised signal by a high-pass filter. The corner frequency fof the high-pass filter is adjusted such that the output amplitude of the audio signal at the end of the processing segment is equal or proportional to the input amplitude of the audio signal.

Circuit for improving the intelligibility of audio signals containing speech

A system for decoding an electrical input signal includes a filter that impresses a variable gain on a portion of the input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.

Adaptive signal weighting system

A circuit for processing an input audio signal received at an input of the circuit provides a processed audio signal at a circuit output. The circuit includes first and second conductive paths through which the received audio signal travels. The audio signal is processed such that harmonics of the signal components with a low-frequency are generated in the second path and are admixed to the signal in the first path. In the second path the audio signal is sequentially bandpass filtered, weighted with a correction factor, amplified, limited to a predetermined value, and bandpass filtered, where the correction factor is reduced when the predetermined value is exceeded.

Apparatus and method for processing an audio signal to compensate for the frequency response of loudspeakers

The invention relates to a method and a device for converting a digital, pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein the digital signal PCM, f(t) is multiplied by at least one derivative (f'(t), f&#x2033;(t), . . . , f(t)) of the signal (f(t)). The invention also relates to a technique for converting a digital pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein to obtain a sampling rate sufficient for the pulse-width-modulated signal an oversampling of the digital signal is implemented with a first oversampling factor before the conversion and an second oversampling factor after the conversion, such that the product of the oversampling factors before and after conversion of the digital signal to the pulse-width-modulated signal corresponds at least to the value of the required oversampling factor.

PCM-to-PWM converter

A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.

Apparatus and method and decoding biphase signals

Noise that is normally generated during the switching of a noise shaper may be reduced by switching the noise shaper to an inactive or off state after the occurrence of one or more predetermined criteria, for example the detection of a predetermined number of data values below a threshold value or equal to a certain value, or of a predetermined number of data values within a threshold region about a value that is constant with respect to the data values.

Noise shaper circuit and method for reducing switching noise

A device for detecting and suppressing noise includes a noise detection device that receives and processes an input signal to determine if the input signal contains noise and provides a detected noise signal indicative of whether or not noise is detected in the input signal. A noise filter receives the input signal and when the detected noise signal does not indicate the presence of noise the noise filter provides an output signal equal to input signal. When the detected noise signal indicates the presence of noise the noise filter processes the input signal through a first filter to provide a filtered signal such that the output signal is equal to the filtered signal. The noise filter comprises a control circuit that receives the input signal and the filtered signal and in response dynamically adjusts a cut-off frequency control signal that controls a cut-off frequency of the first filter.

Device and method for detecting and suppressing noise

A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d) is derived. From this, associated bit combinations (StStStp) are determined, and a decision is made as to whether the respective bit combination (StStStp) is a valid combination (SgSgSgp) or an erroneous one (SfSfSfp). Probability values (SwSwSwp) are determined that decide which parts of the erroneous bit combination (SfSfSfp) are probably true and/or which are probably false. Next, a corrected bit combination (SkSkSkp) is formed from the existing information. Finally, a second digital signal (d) is generated as an output signal, whose data states are formed either from the valid bit combination (SgSgSgp) or from the corrected bit combination (SkSkSkp).

Method for decoding biphase signals

A system for decoding an electrical input signal includes a filter that impresses a variable gain on the portion of input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.

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Denzlingen, Germany

Matthias Vierthaler