Ams Ag

Austriamicrosystems Ag

Ams International Ag

Ams Age

Matthias Steiner

Thomas Carl Fröhlich

Andreas Fitzi

Richard Forsyth

Nigel Greer

Thomas Fröhlich

Greer Nigel

A baseline restorer circuit including a controller; a sample control circuit arranged to receive an input voltage signal that is output from a circuit stage comprising an amplifier, and configured to capture a sample of the input voltage signal at a sampling time in response to receiving a control signal from the controller; an analogue processing stage to receive the sample and a constant baseline reference voltage and selectively process the sample to provide an output voltage; a transconductance stage to convert the output voltage to a compensation current and supply the compensation current to an input of the circuit stage; and a change detector to monitor if the input voltage signal changes during a time interval around the sampling time, and if no change is detected in the input voltage signal during the time interval, the controller is configured to control the analogue processing stage to process the sample.

Baseline restorer circuit

A transconductor circuitry () with adaptive biasing comprises a first input terminal (E) to apply a first input signal (inp), and a second input terminal (E) to apply a second input signal (inn). A control circuit () is configured to control a first controllable current source () in a first current path () and a second controllable current source () in a second current path () in response to at least one of a first potential of a first node (N) of the first current path () and a second potential of a second node (N) of the second current path (). The first node (N) is located between a first transistor () and the first controllable current source (), and the second node (N) is located between a second transistor () and the second controllable current source ().

Transconductor circuitry with adaptive biasing

A sensor arrangement () comprises an amplifier () having a signal input () to receive an input signal (SIN) and a signal output () to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement () comprises a feedback path connecting the signal output () to the gnal input (), wherein the feedback path comprises a series connection of a capacitive sensor () and a feedback capacitor (). A voltage source arrangement () of the sensor arrangement () is connected to a feedback node () between the capacitive sensor () and the feedback capacitor ().

Sensor arrangement with a capacitive sensor and method for generating an amplified sensor signal with a capacitive sensor

An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.

Amplifier arrangement and switched capacitor integrator

A sensor arrangement () comprises an amplifier () having a signal input () to receive an input signal (SIN) and a signal output () to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement () comprises a feedback path connecting the signal output () to the signal input (), wherein the feedback path comprises a series connection of a capacitive sensor () and a feedback capacitor (). A voltage source arrangement () of the sensor arrangement () is connected to a feedback node () between the capacitive sensor () and the feedback capacitor ().

A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output, and a feedback path that couples the signal output to the signal input, wherein the feedback path includes an anti-parallel circuit of diodes, and a voltage divider including a first and a second divider resistor and a voltage divider tap between the first and the second divider resistor, wherein the voltage divider couples the signal output to a reference potential terminal, and the voltage divider tap is coupled to the anti-parallel circuit of diodes and the anti-parallel circuit of diodes is coupled to the signal input.

Sensor amplifier arrangement and method of amplifying a sensor signal

A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output to provide an amplified sensor signal, and a feedback path that couples the signal output to the signal input and provides a feedback current that is an attenuated signal of the amplified sensor signal and is inverted with respect to the sensor signal.

Sensor amplifier arrangement and method for amplification of a sensor signal

A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Signal processing arrangement and signal processing method, particularly for electronic circuits

A transmitter (TX) for transmitting a pulse density modulated signal comprises means (SDM) for generating a pulse density modulated input signal (SI) and an encoder (ENC). The encoder (ENC) comprises a first input for receiving the pulse density modulated input signal (SI) and a second input for receiving additional information (AI) comprising at least one data bit. The encoder (ENC) is configured to generate a multi-bit telegram (TG) on the basis of the additional information (AI), the telegram (TG) comprising a predefined bit-sequence, and to replace an appropriate number of consecutive bits of the input signal (SI) with the telegram (TG) in order to generate an output signal (SO).

Transmitter and receiver for pulse density modulated signals and signal processing method

A sigma-delta converter comprises a sigma-delta modulator (SDM) with a signal processing block (SP) and a quantizer (QNT), as well as a stage adaptation element (DCC). The signal processing block (SP) is designed for deriving a modulated signal (MOD) in dependence on the respective signals at a signal input (SIN) and at a feedback input (FIN). The quantizer (QNT) comprises a quantization input (QIN) that is coupled to the signal output (SOT) and a quantization output (QOT) that is coupled to the feedback input (FIN), wherein the quantizer is designed for deriving a first quantized signal (Q) from the modulated signal (MOD) by quantization with a first number of stages and for outputting this first quantized signal at the quantization output (QOT). The stage adaptation element is coupled to the quantization output (QOT) on the input side and to a converter output (COT) on the output side and is designed for deriving a second quantized signal (Q) with a second number of stages that is smaller than the first number of stages from the first quantized signal (Q).

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Seiersberg, Austria

Matthias Steiner