Infineon Technologies Ag

Infineon Technologies Austria Ag

Siemens Aktiengesellschaft

Infineon Technology Ag

Matthias Stecher

Khalil Hosseini

Werner Schwetlick

Franz Hirler

Gerald Deboy

Martin Feldtkeller

Armin Willmeroth

Rolf Weis

Peter Nelle

Andreas Zankl

Ralf Otremba

Andreas Peter Meiser

Josef Hoeglauer

Joost Adriaan Willemen

Ulrich Glaser

Markus Menath

Thomas Laska

Magnus-Maria Hell

Yiqun Cao

Michael Mayerhofer

Julien Lebon

Tim Gutheit

Tobias Smorodin

Hans-Joachim Schulze

Joachim Mahler

Hans Weber

Harald Gossner

Rainald Sander

Martin Kerber

Hermann Gruber

Michael Asam

Markus Winkler

Lincoln O'Riain

Renate Hofmann

Joerg Busch

Birgit Von Ehrenwall

Gregory Bellynck

Wolfgang Werner

Xaver Schloegel

Joachim Weyers

Werner Robl

Thomas Christian Neidhart

Thomas Gutt

Roman Roth

Thorsten Hinderer

Michael Melzl

Dirk Siepe

Markus Muellauer

Anja Reitmeier

Thomas Neidhart

Martin Kotzbauer

Julie Mathilde Suzanne Paye

Anja Gisslbl

Karsten Mosig

Hermann Peri

A device including a first voltage domain and a second voltage domain is provided, the voltage domains being separated by an isolation barrier. In addition, the device includes a scratch detection circuit including a first and a second electrode at a distance of less than 2 &#x3bc;m.

Device comprising two voltage domains and method

In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.

Semiconductor device, electronic component and method

One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.

Semiconductor device with multi-layer metallization

A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*10&#x3a9;m and less than 1*10&#x3a9;m.

Semiconductor devices and methods for forming semiconductor devices

A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.

Semiconductor component comprising copper metallizations

A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.

Vertical transistor with improved robustness

A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

Method for producing a conductor line

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than &#x2212;10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than &#x2212;10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

Integrated circuit having an ESD protection structure and photon source

An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Electronic device and method for production

A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

Method of triggering avalanche breakdown in a semiconductor device

One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Semiconductor structure including guard ring

Growing community of inventors

Munich, Germany

Matthias Stecher