Advanced Micro Devices Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Globalfoundires Inc.

Matthias Lehr

Frank G Kuechenmeister

Joerg Hohage

Michael Grillberger

Kai Frohberg

Volker Kahlert

Matthias Schaller

Eckhard Langer

Moritz Andreas Meyer

Ralf Richter

Christoph Schwan

Holger S Schuehrer

Frank Koschinsky

J&uuml;rgen Lindolf

Frank Seliger

Albrecht Kieslich

Dirk Breuer

Jochen M&uuml;ller

Maik Liebau

Marcel Wieland

Rene Tews

Axel Walter

Frank Feustel

Thomas Werner

Dominique Savignac

Daniel Fischer

Juergen Boemmels

Carsten Peters

Axel Brintzinger

Martin Mazur

Christian Zistl

Heike Salz

Andreas Ott

Tobias Letz

Veronika Polei

Volker Grimm

Thomas Melde

Martin O'Toole

Gotthard Jungnickel

Stefan Dankowski

Ulrich Frey

Peter Huebler

Sven Mueller

Lothar Bauch

Holm Geisler

Rainer Giedigkeit

Alexander Platz

Thomas Zell

Moritz-Andreas Meyer

Wolfgang Leiberg

Uwe Schilling

Kamel Ayadi

Lothar Mergili

Thomas Herrmann

Irene Sperl

Jens M&ouml;ckel

Dirk T&ouml;bben

Peter Thieme

Gregoire Grandremy

Jochen Hanebeck

Torsten Werneke

J&uuml;rgen Pahlitzsch

Lars Voland

Jens Hassmann

Rakesh Kumar Kuncha

Steffi Thierbach

Kornelia Dittmar

Jochen Klais

Steffen Koch

Eva Ebertseder

A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

Semiconductor device comprising a die seal including long via lines

The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a 'long' via line feature, superior sensitivity for variations of depth of focus may be achieved.

A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

Metal line layout based on line shifting

Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.

Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating same

A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 &#x3bc;m may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Semiconductor device including a stress buffer material formed above a low-k metallization system

When forming sophisticated semiconductor devices including metal pillars arranged on contact pads, which may comprise aluminum, device performance and reliability may be improved by avoiding exposure of the contact pad material to the ambient atmosphere, in particular during and between dicing and packaging processes. To this end, the contact pad material may be covered by a protection layer or may be protected by the metal pillars itself, thereby concurrently improving mechanical stress distribution in the device.

Semiconductor device with improved metal pillar configuration

In semiconductor devices, the alignment mark for performing alignment processes of measurement tools and the like may be positioned within the die seal area on the basis of a geometric configuration, which still preserves mechanical integrity of the die seal without compromising the spatial information encoded into the alignment marks. For example, L-shaped alignment marks may be provided at one or more corners of the die seal area.

Semiconductor device comprising a die seal having an integrated alignment mark

In a semiconductor device or test structure, appropriate heating elements, for instance in the form of resistive structures, are implemented so as to obtain superior area coverage, thereby enabling a precise evaluation of the thermal conditions within a complex semiconductor device. In particular, the device internal heating elements may allow the evaluation of hot spots and the response of a complex metallization system to specific temperature profiles, in particular at critical areas, such as edge regions in which mechanical stress forces are typically highest in contact regimes in which the package substrate and the metallization system are directly connected.

Assessing thermal mechanical characteristics of complex semiconductor devices by integrated heating systems

By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be 'simulated,' thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

Technique for forming a passivation layer without a terminal metal

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.

Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance

Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability.

Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques

In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.

Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime

The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed.

Assessing metal stack integrity in sophisticated semiconductor devices by mechanically stressing die contacts

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

Stress reduction in chip packaging by using a low-temperature chip-package connection regime

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Dresden, Germany

Matthias Lehr