Infineon Technologies Ag

Infineon Technologies Austria Ag

Matthias Kuenle

Hans-Joachim Schulze

Johannes Baumgartl

Daniel Schloegl

Christoph Weiss

Francisco Javier Santos Rodriguez

Ravi Keshav Joshi

Juergen Steinbrenner

Gerhard Schmidt

Alexander Breymesser

Stephan Voss

Georg Ehrentraut

Andreas Moser

Erwin Lercher

Roland Rupp

Martin Poelzl

Matteo Dainese

Bernhard Goller

Helmut Oefner

Markus Kahn

Martin Sporn

Andreas Haghofer

Christoph Gruber

Christian Illemann

Ralf Siemieniec

Hans Weber

Manfred Engelhardt

Christian Philipp Sandow

Michael Hutzler

Wolfgang Roesner

Ingo Muri

Erich Griebl

Carsten Schaeffer

Daniel Tutuc

Olaf Storbeck

Sokratis Sgouridis

Michael Knabl

Oana Julia Spulber

Olaf Fiedler

Mathias Male

Thomas Huber

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Methods for forming a semiconductor device having a second semiconductor layer on a first semiconductor layer

A processing chamber includes a chamber body, a substrate support configured to hold a substrate in place, and a pre-heat ring having a central opening sized to be disposed around the substrate. A process gas inlet is configured to direct process gas in a lateral direction to flow over the pre-heat ring and the substrate. A process gas flow deflector includes a radially outer mounting portion and a radially inner blade-shaped process gas deflection portion extending in a radial direction. The radially inner blade-shaped process gas deflection portion is shaped as a ring segment. The radially inner blade-shaped process gas deflection portion is disposed above the process gas inlet and dimensioned to overlap with the pre-heat ring, wherein a degree of overlap between the pre-heat ring and process gas flow deflector in the radial direction is at least ½ of the radial dimension of the pre-heat ring.

Substrate processing chamber and process gas flow deflector for use in the processing chamber

Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Method for producing a superjunction device

A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050&#xb0; C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

Methods for forming a semiconductor device

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

Method for processing a semiconductor wafer, semiconductor composite structure and support structure for semiconductor wafer

A CVD reactor, including a deposition chamber housing a first susceptor and a second susceptor, the first susceptor having a cavity for receiving a first substrate, the first substrate having a front surface and a back surface, the second susceptor having a cavity for receiving a second substrate, the second substrate having a front surface and a back surface, and the first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel.

Apparatus and method for chemical vapor deposition process for semiconductor substrates

An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 10cmalong a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.

Insulated gate bipolar transistor having first and second field stop zone portions and manufacturing method

An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

Method for manufacturing a semiconductor device

A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 10/cm; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.

Method for manufacturing a power semiconductor device having a reduced oxygen concentration

A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*10cmfor at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*10cm, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.

Method of manufacturing a power semiconductor device

A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

Buried insulator regions and methods of formation thereof

According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

Semiconductor wafer and method for processing a semiconductor wafer

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

Producing a semiconductor device by epitaxial growth

A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*10cmfor at least 5% of the total extension of the transition region in the extension direction.

Power semiconductor device

Growing community of inventors

Villach, Austria

Matthias Kuenle