Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Matthias Kroenke

Stefan Tegen

Igor Kasko

Alessandro Ferrara

Franz Hirler

Rolf Weis

Thomas Mikolajick

Adrian Finney

Werner Graf

Kae-Horng Wang

Wolfgang Gustin

Andrei Josiek

Thomas Dittkrist

Christoph Kubasch

A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.

Transistor device

The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Semiconductor die with a power device and method of manufacturing the same

A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

Transistor device having a field plate

Transistor device having a field plate in an elongate active trench

In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

Transistor device and method of forming a field plate in an elongate active trench of a transistor device

The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarization. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.

Method of treating a structured surface

The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate () is provided with at least one first, second and third gate stack (GS, GS, GS) of approximately the same height surface of said substrate, a common active area () being provided on the surface of the substrate in said substrate () between the first and second gate stack (GS, GS); a first insulating layer () is provided in order to cover the embedding of the first second and third gate stack (GS, GS, GS); the upper side of a gate connection () of the third gate stack (GS) is uncovered; a second insulating layer () is provided in order to cover the upper side of a gate connection (); a mask (M) is provided on the resulting structure having a first opening () above the uncovered upper side of the gate connection () of the third gate stack (GS), a second opening (F) above the substrate () between the third and second gate stack (GS, GS) and a third opening (F) above the common active area (), partially overlapping the first and second gate stack (GS, GS), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask () in an etching process, the first contact hole (KB) uncovering the common active area () on the surface of the substrate between the first and second gate stack (GS, GS), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS, GS) and the third contact hole (KG) uncovering the upper side of the gate connection () of the third gate stack (GS).

Method for the production of an integrated circuit

The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

Method for producing ferroelectric capacitors and integrated semiconductor memory chips

Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.

Growing community of inventors

Dresden, Germany

Matthias Kroenke