Dspace Digital Signal Processing and Control Engineering Gmbh

Dspace Gmbh

Matthias Klemm

Robert Leinfellner

Robert Polnau

Jochen Sauer

Matthias Schmitz

Thorsten Brehm

Andreas Himmler

Daniel Baldin

A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.

Method for synchronizing a checking apparatus, and a checking apparatus and a composite system comprising at least two checking apparatuses

A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.

Inspection device

A system for testing at least a first automatic control device via a plant model includes: a first subsystem; and a second subsystem which is spatially separated from the first subsystem. The plant model comprises an executable first model code and an executable second model code. The first subsystem comprises a first time-signal processing component configured to electronically assign a first time signal (Ts) from a global time source to a first event. The first model code is configured to provide a first calculation result based on the first event. The second subsystem comprises a second time-signal processing component configured to electronically assign a second time signal (Ts) from the global time source to a second event. The second model code is configured to provide a second calculation result based on the second event.

Apparatus and method for testing an automatic control device

An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.

Interface unit for routing prioritized input data to a processor

A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.

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Paderborn, Germany

Matthias Klemm