International Business Machines Corporation

Globalfoundries Inc.

Matthias Klein

Sascha Junghans

Norbert Hagspiel

Anthony Thomas Sofia

Jonathan D Bradbury

Christoph Raisch

Marco Kraemer

Christian Jacobi

Eric N Lais

David F Craddock

Bruce C Giamei

Peter Grimm Sutton

Ashutosh Misra

Girish Gopala Kurup

Joerg H Walter

Mark S Farrell

Peter Dana Driever

Brenton F Belmar

Ekaterina M Ambroladze

Carsten Otte

Simon Weishaupt

Robert J Sonnelitter, Iii

Frank Siegfried Lehnert

Timothy John Slegel

Bulent Abali

Michael F Fee

Gary E Strait

Timothy J Siegel

Matthew J Kalos

Craig Raymond Walters

Thomas Schlipf

Edward W Chencinski

Harry M Yudenfriend

Pak-kin Mak

Louis P Gomes

Timothy Carl Bronson

Vesselina K Papazova

Garrett M Drapala

Deepankar Bhattacharjee

Ashutosh Mishra

Donald W Schmidt

Anthony Saporito

Wolfgang Roesner

Bruce H Ratcliff

Gregory William Alexander

Beth A Glendening

Bernd Nerz

Michael James Becht

Arthur J O'Neill

Einar Lueck

Arun Joseph

Christian Borntraeger

Andreas Wagner

Ralf Winkelmann

Tu-An T Nguyen

Dominik Dingel

Scott A Brewer

Jason D Kohl

Manfred Walz

Heiko Carstens

Mahmoud Amin

Thomas Buechner

Gerhard Zilles

Jörg-Stephan Vogt

Shashidhar Reddy

Kevin Lopes

Hanno Eichelberger

Sampath Goud Baddam

Hubertus Franke

Michael Andrew Blake

Ulrich Mayer

Martin Eckert

Scott Barnett Swaney

Damir Anthony Jamsek

Wilhelm Ernst Haller

Kenneth Douglas Klapproth

Preetham M Lobo

Hieu Trong Huynh

Brad D Stilwell

Hanno Ulrich

Deanna P D Berger

Chad G Wilson

Stefan Usenbinz

Tim Bronson

George Diedrich Gristede

Friedhelm Kessler

Robert W St John

Winston Herring

Lahiruka Winter

Darwin W Norton, Jr

Alia Shah

Sajay Mathew Karottukottarathil Baby

Julian Heyne

Fahmiyah Samad

Ananth Garikapati

Jeorg Walter

Bruce Conrad Giamei

A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

Input/output (I/O) store protocol for pipelining coherent operations

A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

System for collaborative hardware RTL logic timing debug in integrated circuit designs

A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

Technique to handle insufficient on-chip memory capacity in decompressors

Combining PCIe partial store commands along cache line boundaries, including: receiving a plurality of Peripheral Component Interface express (PCIe) packets; splitting the plurality of PCIe packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.

Combining peripheral component interface express partial store commands along cache line boundaries

Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Decentralized hot cache line tracking fairness mechanism

Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Preemptive tracking of remote requests for decentralized hot cache line fairness tracking

An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Handling an input/output store instruction

An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization with running indicator

The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

Heterogeneous services for enabling collaborative logic design and debug in aspect oriented hardware designing

An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.

Extended asynchronous data mover functions compatibility indication

Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

Controller address contention assumption

A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.

Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment

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Wappingers Falls, NY, United States of America

Matthias Klein