Infineon Technologies Ag

Apple Inc.

Lantiq Beteiligungs Gmbh & Co. Kg

Matthias Heink

Raimar Thudt

Andreas Foglar

Charles Bry

Friedrich Geissler

Mirko Sauermann

Taro Kamiko

Martin Erdmann

Michael Gerling

Franz-Josef Schaefer

Constantin Daniel Ciortescu

Vanja Rados

Franz-Josef Schafer

Soeren Sonntag

The present disclosure describes a device including an initiator, a target, a communication bus coupling the initiator to the target over a channel, a functional circuit, and an error logger circuit. The functional circuit is coupled to the channel and can perform a function associated with a transaction request from the initiator to the target. The functional circuit can include an error detection circuit to detect an error associated with the function performed by the functional circuit and to generate an error indicator signal to indicate that the error has been detected. The error logger circuit can be coupled to the functional circuit, in which the error logger circuit is configured to receive the error indicator signal from the error detection circuit and store information about the error.

Error logger circuit

Implementations related to detecting control data are presented herein. A detector searches for control data in a first set of pre-determined control data, wherein a respective subset of the first set is assigned to a respective logical port and the respective subset is excluded from the first set when searching for the control data received from the respective logical port.

Detector to search for control data

In a method for classifying data packet units, each comprising a group of data packet parameters which comprises a plurality of data packet parameters, a subgroup of data packet parameters for configuring a classification key is selected, the data packet units are divided into data packet classes on the basis of the classification key and a selected classification algorithm, and the data packet units are allocated to further data packet parameters which correspond to the respective data packet class.

Method and processor for classifying data packet units

An ATM-port module for an ATM-node having an Ethernet switch includes an ATM-controller; and an Ethernet-switch interface connecting it to the Ethernet switch. The switch has an Ethernet encapsulating-unit for encapsulating ATM cells processes by the ATM-controller into packets for transmission to the switch, and an Ethernet decapsulating-unit for extracting ATM cells from packets received from the switch. The module further includes a segmentation-and-reassembly unit; and a buffering-and-scheduling unit. The buffering-and-scheduling unit provides a processed enlarged-ATM-cell to the encapsulating-unit when an indication flag indicates that an ATM port is a destination port of the enlarged ATM-cell; and a processed enlarged-ATM-cell to the segmentation-and-reassembly unit when an indication flag indicates that an Ethernet port is the enlarged ATM-cell's destination port.

ATM-port with integrated ethernet switch interface

Growing community of inventors

Munich, Germany

Matthias Heink