Menara Networks, Inc.

Matthias Bussmann

Salam Elahmadi

Lloyd Frederick Linder

Harry Tan

Kelvin Tran

Denis Zelenin

Dalius Baranauskas

One embodiment of the invention features a programmable gain stage in analog update circuitry to overcome the accuracy limitation of the circuit gain and the maintenance of small finite number of possible sequence estimates.

Calibration method and circuit for an add-compare-select loop

According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.

Summing circuit for a filter

According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.

Analog finite impulse response filter

According to one embodiment of the invention, a circuit comprising a plurality of operational transconductance amplifiers (OTAS) is described. The first OTA has differential input and differential output. The second OTA also has differential input, where a first output of the first OTA is coupled to the first differential input of the second OTA, which is an inverting input. A second output of the first OTA is coupled to the second input of the second OTA, which is a non-inverting input. The first differential output being coupled to a first input of the first OTA and the second differential output being coupled to a second input of the first OTA for negative feedback and current biasing.

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Los Angeles, CA, United States of America

Matthias Bussmann